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反转FSMC信号电平，尝试测试

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This commit is contained in:
RuigeLee
2024-03-06 17:41:28 +08:00
parent ea226e913a
commit ca60205abc
2 changed files with 30 additions and 30 deletions
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24
src/main/scala/backBoard/BackBoardMst.scala
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@@ -11,10 +11,10 @@ class FSMC_Port_Bundle extends Bundle{
val ADIn = Input(UInt(16.W))
val ADOut = Output(UInt(16.W))
val ADOEn = Output(Bool())
val cs = Input(Bool())
val rd = Input(Bool())
val wr = Input(Bool())
val adv = Input(Bool())
val csn = Input(Bool())
val rdn = Input(Bool())
val wrn = Input(Bool())
val advn = Input(Bool())
}
@@ -120,10 +120,10 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
withClockAndReset( io.ides_pclk.asClock, reset ){//100M
val fsmcCSSync = ShiftRegisters( io.FSMC.cs, 3, false.B, true.B )
val fsmcRDSync = ShiftRegisters( io.FSMC.rd, 3, false.B, true.B )
val fsmcWRSync = ShiftRegisters( io.FSMC.wr, 3, false.B, true.B )
val fsmcADVSync = ShiftRegisters( io.FSMC.adv, 3, false.B, true.B )
val fsmcCSSync = ShiftRegisters( ~io.FSMC.csn, 3, false.B, true.B )
val fsmcRDSync = ShiftRegisters( ~io.FSMC.rdn, 3, false.B, true.B )
val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B )
val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )
io.FSMC.ADOEn := fsmcRDSync(1)
@@ -135,8 +135,8 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val regOut = Wire(UInt(16.W))
val fsmcCSWRSync = ShiftRegisters( io.FSMC.cs & io.FSMC.wr, 3, false.B, true.B )
val fsmcCSRDSync = ShiftRegisters( io.FSMC.cs & io.FSMC.rd, 3, false.B, true.B )
val fsmcCSWRSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.wrn, 3, false.B, true.B )
val fsmcCSRDSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.rdn, 3, false.B, true.B )
@@ -257,8 +257,8 @@ trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
abstract class BackBoardMstLVDSBase extends BackBoardMstBase
// with BackBoardMstFSMC
with BackBoardMstSim
with BackBoardMstFSMC
// with BackBoardMstSim
{