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Mst调试用屏蔽FSMC

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This commit is contained in:
RuigeLee
2024-10-24 10:02:24 +08:00
parent 5d5fce6747
commit c6099dba70
1 changed files with 31 additions and 20 deletions
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17
src/main/scala/backBoard/shin/ShinMst.scala
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@@ -81,12 +81,23 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
require( headByte == 8 ) require( headByte == 8 )
val testIOShift = ShiftRegisters(io.testIO, headByte/2 + 1, false.B, true.B) val testIOShift = ShiftRegisters(io.testIO, headByte/2 + 1, false.B, true.B)
val sendHeader = Reg( new Header_Info_Bundle )
val sendHead = sendHeader.asUInt
val cdrPendBuf = Module( new Queue( new AXIS_Bundle(8), 1, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance) //Timing Opt val cdrPendBuf = Module( new Queue( new AXIS_Bundle(8), 1, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance) //Timing Opt
cdrOut.io.axis <> cdrPendBuf.io.deq cdrOut.io.axis <> cdrPendBuf.io.deq
val sendHeader = Wire( new Header_Info_Bundle )
sendHeader.length := 512.U
sendHeader.operator := 0.U
sendHeader.param(0) := 0.U
sendHeader.param(1) := 0.U
sendHeader.param(2) := 0.U
val sendHead = sendHeader.asUInt
/*
val sendHeader = Reg( new Header_Info_Bundle )
val sendHead = sendHeader.asUInt
when( ~testIOShift(0) & io.testIO ){ when( ~testIOShift(0) & io.testIO ){
@@ -110,7 +121,7 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
} .elsewhen( ~testIOShift(4) & testIOShift(3) ){ } .elsewhen( ~testIOShift(4) & testIOShift(3) ){
sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle) sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
} }
*/