diff --git a/src/main/scala/backBoard/shin/ShinMst.scala b/src/main/scala/backBoard/shin/ShinMst.scala
index 97f6849..45e9797 100644
--- a/src/main/scala/backBoard/shin/ShinMst.scala
+++ b/src/main/scala/backBoard/shin/ShinMst.scala
@@ -81,36 +81,47 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
   require( headByte == 8 )
 
   val testIOShift = ShiftRegisters(io.testIO, headByte/2 + 1, false.B, true.B)
-  val sendHeader = Reg( new Header_Info_Bundle )
-  val sendHead = sendHeader.asUInt
 
   val cdrPendBuf = Module( new Queue( new AXIS_Bundle(8), 1, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance) //Timing Opt
   cdrOut.io.axis <> cdrPendBuf.io.deq
 
+                val sendHeader = Wire( new Header_Info_Bundle )
+                sendHeader.length   := 512.U
+                sendHeader.operator := 0.U
+                sendHeader.param(0)   := 0.U
+                sendHeader.param(1)   := 0.U
+                sendHeader.param(2)   := 0.U
+                val sendHead = sendHeader.asUInt
+
+/*
+
+                val sendHeader = Reg( new Header_Info_Bundle )
+                val sendHead = sendHeader.asUInt
 
 
-  when( ~testIOShift(0) & io.testIO ){
-    mirrorReg.io.addrB  := 0.U
-    mirrorReg.io.enrB   := true.B
-  } .elsewhen( ~testIOShift(1) & testIOShift(0) ){
-    mirrorReg.io.addrB  := 1.U
-    mirrorReg.io.enrB   := true.B
 
-    sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
-  } .elsewhen( ~testIOShift(2) & testIOShift(1) ){
-    mirrorReg.io.addrB  := 2.U
-    mirrorReg.io.enrB   := true.B
+                when( ~testIOShift(0) & io.testIO ){
+                  mirrorReg.io.addrB  := 0.U
+                  mirrorReg.io.enrB   := true.B
+                } .elsewhen( ~testIOShift(1) & testIOShift(0) ){
+                  mirrorReg.io.addrB  := 1.U
+                  mirrorReg.io.enrB   := true.B
 
-    sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
-  } .elsewhen( ~testIOShift(3) & testIOShift(2) ){
-    mirrorReg.io.addrB  := 3.U
-    mirrorReg.io.enrB   := true.B
+                  sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
+                } .elsewhen( ~testIOShift(2) & testIOShift(1) ){
+                  mirrorReg.io.addrB  := 2.U
+                  mirrorReg.io.enrB   := true.B
 
-    sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
-  } .elsewhen( ~testIOShift(4) & testIOShift(3) ){
-    sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
-  }
+                  sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
+                } .elsewhen( ~testIOShift(3) & testIOShift(2) ){
+                  mirrorReg.io.addrB  := 3.U
+                  mirrorReg.io.enrB   := true.B
 
+                  sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
+                } .elsewhen( ~testIOShift(4) & testIOShift(3) ){
+                  sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
+                }
+*/