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增加主站offset寄存器用于多个主站校准时间

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This commit is contained in:
RuigeLee
2025-09-03 11:23:57 +08:00
parent 864a7d3d23
commit c5d193a1bc
1 changed files with 30 additions and 26 deletions
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56
src/main/scala/backBoard/shin/Interface.scala
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@@ -122,6 +122,7 @@ class MasterRegisterBundle extends Bundle{
val isRecCRCErr = UInt(4.W)
val rplTimeStampTx = UInt(16.W)
val timeStampOffset = UInt(64.W)
}
@@ -476,14 +477,14 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === "h146".U ) -> cReg.syncOffset(3)(23,16),
(addr === "h147".U ) -> cReg.syncOffset(3)(31,24),
// (addr === "h148".U ) -> 0.U,//cReg.localPoint(7,0),
// (addr === "h149".U ) -> 0.U,//cReg.localPoint(15,8),
// (addr === "h14a".U ) -> 0.U,//cReg.localPoint(23,16),
// (addr === "h14b".U ) -> 0.U,//cReg.localPoint(31,24),
// (addr === "h14c".U ) -> 0.U,//cReg.localPoint(39,32),
// (addr === "h14d".U ) -> 0.U,//cReg.localPoint(47,40),
// (addr === "h14e".U ) -> 0.U,//cReg.localPoint(55,48),
// (addr === "h14f".U ) -> 0.U,//cReg.localPoint(63,56),
(addr === "h148".U ) -> mReg.timeStampOffset(7,0),
(addr === "h149".U ) -> mReg.timeStampOffset(15,8),
(addr === "h14a".U ) -> mReg.timeStampOffset(23,16),
(addr === "h14b".U ) -> mReg.timeStampOffset(31,24),
(addr === "h14c".U ) -> mReg.timeStampOffset(39,32),
(addr === "h14d".U ) -> mReg.timeStampOffset(47,40),
(addr === "h14e".U ) -> mReg.timeStampOffset(55,48),
(addr === "h14f".U ) -> mReg.timeStampOffset(63,56),
) ++
( 0 until 128 ).map{ i =>
@@ -785,6 +786,8 @@ trait InterfaceSync{ this: InterfaceBase =>
cReg.syncWidth(i) := syncWidth(i)
}
val timeStampOffset = RegInit(0.U(64.W)); mReg.timeStampOffset := timeStampOffset
val timeStampOffset_WRCopy = RegInit(0.U(64.W))
val syncPoint = RegInit("hFFFFFFFFFFFFFFFF".U(64.W)); cReg.syncPoint := syncPoint
val syncPoint_WRCopy = RegInit("hFFFFFFFFFFFFFFFF".U(64.W))
val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
@@ -836,23 +839,24 @@ trait InterfaceSync{ this: InterfaceBase =>
syncPeroid := Cat( dataw, syncPeroid(23,0) )
}
// .elsewhen( addrw === "h148".U ){
// localPoint := Cat( localPoint(63,8), dataw )
// } .elsewhen( addrw === "h149".U ){
// localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) )
// } .elsewhen( addrw === "h14a".U ){
// localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) )
// } .elsewhen( addrw === "h14b".U ){
// localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) )
// } .elsewhen( addrw === "h14c".U ){
// localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) )
// } .elsewhen( addrw === "h14d".U ){
// localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) )
// } .elsewhen( addrw === "h14e".U ){
// localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) )
// } .elsewhen( addrw === "h14f".U ){
// localPoint := Cat( dataw, localPoint(55,0) )
// }
.elsewhen( addrw === "h148".U ){
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,8), dataw )
} .elsewhen( addrw === "h149".U ){
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,16), dataw, timeStampOffset_WRCopy(7,0) )
} .elsewhen( addrw === "h14a".U ){
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,24), dataw, timeStampOffset_WRCopy(15,0) )
} .elsewhen( addrw === "h14b".U ){
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,32), dataw, timeStampOffset_WRCopy(23,0) )
} .elsewhen( addrw === "h14c".U ){
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,40), dataw, timeStampOffset_WRCopy(31,0) )
} .elsewhen( addrw === "h14d".U ){
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,48), dataw, timeStampOffset_WRCopy(39,0) )
} .elsewhen( addrw === "h14e".U ){
timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,56), dataw, timeStampOffset_WRCopy(47,0) )
} .elsewhen( addrw === "h14f".U ){
timeStampOffset_WRCopy := Cat( dataw, timeStampOffset_WRCopy(55,0) )
timeStampOffset := Cat( dataw, timeStampOffset_WRCopy(55,0) )
}
for( i <- 1 until 4 ){
@@ -931,7 +935,7 @@ trait InterfaceSync{ this: InterfaceBase =>
sReg.deltaFinal := io.deltaFinal
cReg.recoTimeStamp :=
Mux(isMstMode, cReg.timeStamp,
Mux(isMstMode, cReg.timeStamp + mReg.timeStampOffset,
RegNext( cReg.timeStamp + sReg.deltaFinal, 0.U(64.W) )
)
sReg.slvDeltaTime := io.slvDeltaTime