makefile被覆盖,提交新的makefile

2025-09-15 16:58:34 +08:00
parent 2ecb547bc8
commit bffe4fcab1
1 changed files with 1 additions and 0 deletions
--- a/1
+++ b/1
@@ -64,6 +64,7 @@ testShinClk:
 	python3 ./tb/shinTest/check_testcase.py

 testCDR:
+	python3 ./tb/shinTest/gen_sim_cdr_clk.py --clk 0 40
 	iverilog -Wall  \
 	-o ./tb/build/simCDR.iverilog  \
 	-y ./generated/SimCDR \