diff --git a/Makefile b/Makefile
index 3a2860c..8e88c0d 100644
--- a/Makefile
+++ b/Makefile
@@ -64,6 +64,7 @@ testShinClk:
 	python3 ./tb/shinTest/check_testcase.py
 
 testCDR:
+	python3 ./tb/shinTest/gen_sim_cdr_clk.py --clk 0 40
 	iverilog -Wall  \
 	-o ./tb/build/simCDR.iverilog  \
 	-y ./generated/SimCDR \