完成0x300，0x301寄存器实现

src/main/scala/backBoard/shin/Interface.scala

@@ -58,7 +58,7 @@ class CommonRegisterBundle extends Bundle{
 
   val custom = Vec( 128, UInt(8.W) )
 
-
+  val smUsedDepth = Vec(8, UInt(8.W))
   val smTrigLen = Vec(8, UInt(11.W))  //触发SM切换缓冲区的地址 （或读或写）
 
 
@@ -183,6 +183,9 @@ class InterfaceIO extends Bundle{
   val interrupt = Output(Bool())
 
   val wdtTrigger = Input(Vec(17, Bool()))
+
+  val smUsedDepth = Input( Vec(8, UInt(8.W)) )
+  val isSMReset = Output( Vec(8, Bool()) )
 }
 
 
@@ -386,6 +389,9 @@ abstract class InterfaceBase extends Module{
         ( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op,
         ( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable,
       )}.reduce(_++_) ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h301".U(16.W) + (i*4).U) )  -> cReg.smUsedDepth(i)
+      } ++
       ( 0 until 8 ).map{ i =>
         ( addr === ("h302".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
       } ++
@@ -636,6 +642,10 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
 
 
   for( i <- 0 until 8 ){
+
+    io.isSMReset(i) := isEnW & (addrw === ("h300".U(16.W) + (i*4).U))
+
+    cReg.smUsedDepth(i) := io.smUsedDepth(i)
     cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )
 
     when( isEnW & addrw === ("h303".U(16.W) + (i*4).U) ){