From bfb7c05ac4bc7bcfecd0f80edf26930b3930050f Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Tue, 29 Jul 2025 16:51:28 +0800
Subject: [PATCH] =?UTF-8?q?=E5=AE=8C=E6=88=900x300=EF=BC=8C0x301=E5=AF=84?=
 =?UTF-8?q?=E5=AD=98=E5=99=A8=E5=AE=9E=E7=8E=B0?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 12 +++++++++++-
 src/main/scala/backBoard/shin/SMUnit.scala    |  8 ++++++++
 src/main/scala/backBoard/shin/ShinTop.scala   |  6 +++++-
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 401a3ac..c887109 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -58,7 +58,7 @@ class CommonRegisterBundle extends Bundle{
 
   val custom = Vec( 128, UInt(8.W) )
 
-
+  val smUsedDepth = Vec(8, UInt(8.W))
   val smTrigLen = Vec(8, UInt(11.W))  //触发SM切换缓冲区的地址 （或读或写）
 
 
@@ -183,6 +183,9 @@ class InterfaceIO extends Bundle{
   val interrupt = Output(Bool())
 
   val wdtTrigger = Input(Vec(17, Bool()))
+
+  val smUsedDepth = Input( Vec(8, UInt(8.W)) )
+  val isSMReset = Output( Vec(8, Bool()) )
 }
 
 
@@ -386,6 +389,9 @@ abstract class InterfaceBase extends Module{
         ( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op,
         ( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable,
       )}.reduce(_++_) ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h301".U(16.W) + (i*4).U) )  -> cReg.smUsedDepth(i)
+      } ++
       ( 0 until 8 ).map{ i =>
         ( addr === ("h302".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
       } ++
@@ -636,6 +642,10 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
 
 
   for( i <- 0 until 8 ){
+
+    io.isSMReset(i) := isEnW & (addrw === ("h300".U(16.W) + (i*4).U))
+
+    cReg.smUsedDepth(i) := io.smUsedDepth(i)
     cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )
 
     when( isEnW & addrw === ("h303".U(16.W) + (i*4).U) ){
diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala
index dd51fcb..dbdfd8a 100644
--- a/src/main/scala/backBoard/shin/SMUnit.scala
+++ b/src/main/scala/backBoard/shin/SMUnit.scala
@@ -31,6 +31,7 @@ class SMUnitIO(depth: Int) extends Bundle {
   val deq = Input(Bool())
 
   val sram = Flipped(Vec(depth, new SRAM2kIO))
+  val cnt  = Output(UInt(8.W))
 
 }
 
@@ -84,7 +85,14 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
     ( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar
   })
 
+  val cnt = RegInit(0.U((log2Ceil(depth)).W)); io.cnt := cnt
 
+  when( io.enq & ~isFull ){
+    cnt := cnt + 1.U
+  } .elsewhen( io.deq & ~isEmpty ){
+    cnt := cnt - 1.U
+    assert(cnt =/= 0.U)
+  }
 
 }
 
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 4274e3a..555f1ce 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -150,7 +150,11 @@ abstract class ShinTopBase extends Module{
   smUnit(5).io.enq := interface.io.uSMenq(2)
   smUnit(7).io.enq := interface.io.uSMenq(3)
 
-
+  for( i <- 0 until 8 ){
+    interface.io.smUsedDepth(i) := smUnit(i).io.cnt
+    smUnit(i).reset := reset.asBool | interface.io.isSMReset(i)
+    
+  }
 
 
   for( i <- 0 until 4 ){