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使用外部分频器，面积没有变化

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This commit is contained in:
RuigeLee
2024-05-09 11:39:13 +08:00
parent 2ded26a706
commit bfa432a471
3 changed files with 49 additions and 14 deletions
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31
src/main/verilog/di16_top.v
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@@ -25,6 +25,9 @@ wire clk_400m_a;
wire clk_100m_a;
wire clk_50m_a;
wire clk_10m_a;
wire clk_2m_a;
wire clk_500k_a;
wire clk_8us_a;
wire lock_o;
wire reset_stop;
@@ -125,6 +128,33 @@ CLKDIV Inst5_CLKDIVC(
.CLKOUT (clk_10m_a)
);
defparam Inst6_CLKDIVC.DIV_MODE="5";
defparam Inst6_CLKDIVC.GSREN="false";
CLKDIV Inst6_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_10m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_2m_a)
);
defparam Inst7_CLKDIVC.DIV_MODE="4";
defparam Inst7_CLKDIVC.GSREN="false";
CLKDIV Inst7_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_2m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_500k_a)
);
defparam Inst8_CLKDIVC.DIV_MODE="4";
defparam Inst8_CLKDIVC.GSREN="false";
CLKDIV Inst8_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_500k_a),
.CALIB (1'b0 ),
.CLKOUT (clk_8us_a)
);
DIn16 i_din16(
.reset(~rst_n),
.clock(clk_10m_a),
@@ -133,6 +163,7 @@ DIn16 i_din16(
.io_oser_fclk(clk_50m_a),
.io_ides_pclk(clk_100m_a),
.io_ides_fclk(clk_400m_a),
.io_clk8us(clk_8us_a),
.io_lvds_down_din(lvds_down_din),
.io_lvds_down_dout(lvds_down_dout),