From bfa432a47122b098e7fddaa4e412a8b7c0973f7e Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Thu, 9 May 2024 11:39:13 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BD=BF=E7=94=A8=E5=A4=96=E9=83=A8=E5=88=86?=
 =?UTF-8?q?=E9=A2=91=E5=99=A8=EF=BC=8C=E9=9D=A2=E7=A7=AF=E6=B2=A1=E6=9C=89?=
 =?UTF-8?q?=E5=8F=98=E5=8C=96?=
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---
 src/main/scala/backBoard/BackBoardSlv.scala   |  1 +
 src/main/scala/backBoard/LocalRegisters.scala | 31 ++++++++++---------
 src/main/verilog/di16_top.v                   | 31 +++++++++++++++++++
 3 files changed, 49 insertions(+), 14 deletions(-)

diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala
index 7a871d6..4bc42e5 100644
--- a/src/main/scala/backBoard/BackBoardSlv.scala
+++ b/src/main/scala/backBoard/BackBoardSlv.scala
@@ -12,6 +12,7 @@ class BackBoardSlvIO extends Bundle{
   val oser_fclk = Input(Bool())
   val ides_pclk = Input(Bool())
   val ides_fclk = Input(Bool())
+  val clk8us = Input(Bool())
 
   val lvds_down_din  = Input(Bool())
   val lvds_down_dout = Output(Bool())
diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index cb93341..4fc3813 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -60,8 +60,9 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
   }
 
 
-
-  val (usCounter, usTrigger) = Counter(Range(0, 10))
+  val clk16us = withClockAndReset( io.clk8us.asClock, reset ){ Reg(Bool())}
+  withClockAndReset( io.clk8us.asClock, reset ){ clk16us := ~clk16us }
+  // val (usCounter, usTrigger) = Counter(Range(0, 10))
 
 
 }
@@ -71,13 +72,13 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
 
 
 trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
-  val flashCounter = RegInit( 0.U( 19.W ) )
+  val flashCounter = RegInit( 0.U( 15.W ) )
   val flash2HZ = Reg(Bool())
   val flash1HZ = Reg(Bool())
 
 
-  when( usTrigger ){
-    when( flashCounter >= 500000.U ){
+  when( clk16us ){
+    when( flashCounter === 31249.U ){
       flashCounter := 0.U
       flash2HZ := ~flash2HZ
       when( flash2HZ ){
@@ -103,20 +104,21 @@ trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
 trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
 
   val inPin = Wire(UInt(16.W))
-
-
-  val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
-  val flitTrigger = Wire(Vec(9, Bool()))
   val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
-  val digitalIn     = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }
 
 
+  val flitCnt     = withClockAndReset( io.clk8us.asClock, reset ){ RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) )) }
+  val flitTrigger = withClockAndReset( io.clk8us.asClock, reset ){ Wire(Vec(9, Bool())) }
+  val digitalIn   = withClockAndReset( io.clk8us.asClock, reset ){ for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) } }
+
+withClockAndReset( io.clk8us.asClock, reset ){
   flitTrigger(0) := ~RegNext(flitTrigger(0))
 
-  flitTrigger(1) := flitCnt(1) === 15.U
-  when( ~RegNext(usTrigger) & usTrigger ){
-    flitCnt(1) := flitCnt(1) + 1.U      
-  }
+  flitTrigger(1) := clk16us
+  // flitTrigger(1) := flitCnt(1) === 15.U
+  // when( ~RegNext(usTrigger) & usTrigger ){
+  //   flitCnt(1) := flitCnt(1) + 1.U      
+  // }
 
   flitTrigger(2) := flitCnt(2)
   when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
@@ -202,6 +204,7 @@ trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
       }
     }
   }
+}
 
 }
 
diff --git a/src/main/verilog/di16_top.v b/src/main/verilog/di16_top.v
index 66d8caa..ec01b99 100644
--- a/src/main/verilog/di16_top.v
+++ b/src/main/verilog/di16_top.v
@@ -25,6 +25,9 @@ wire clk_400m_a;
 wire clk_100m_a;
 wire clk_50m_a;
 wire clk_10m_a;
+wire clk_2m_a;
+wire clk_500k_a;
+wire clk_8us_a;
 
 wire lock_o;
 wire reset_stop;
@@ -125,6 +128,33 @@ CLKDIV Inst5_CLKDIVC(
   .CLKOUT (clk_10m_a)
 );
 
+defparam Inst6_CLKDIVC.DIV_MODE="5";
+defparam Inst6_CLKDIVC.GSREN="false";
+CLKDIV Inst6_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_10m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_2m_a)
+);
+
+defparam Inst7_CLKDIVC.DIV_MODE="4";
+defparam Inst7_CLKDIVC.GSREN="false";
+CLKDIV Inst7_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_2m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_500k_a)
+);
+
+defparam Inst8_CLKDIVC.DIV_MODE="4";
+defparam Inst8_CLKDIVC.GSREN="false";
+CLKDIV Inst8_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_500k_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_8us_a)
+);
+
 DIn16 i_din16(
   .reset(~rst_n),
   .clock(clk_10m_a),
@@ -133,6 +163,7 @@ DIn16 i_din16(
   .io_oser_fclk(clk_50m_a),
   .io_ides_pclk(clk_100m_a),
   .io_ides_fclk(clk_400m_a),
+  .io_clk8us(clk_8us_a),
 
   .io_lvds_down_din(lvds_down_din),
   .io_lvds_down_dout(lvds_down_dout),