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16bit fsmc data; 16*2 reg, 100us

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This commit is contained in:
RuigeLee
2023-09-08 16:37:31 +08:00
parent 145db92202
commit bf835014bc
4 changed files with 160 additions and 107 deletions
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19
src/main/scala/backBoard/BackBoardSlv.scala
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@@ -36,8 +36,8 @@ abstract class BackBoardSlvBase extends RawModule{
lvdsSlv.io.lvds_up_din := io.lvds_up_din
io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
val downRegWire = Wire(Vec(32, UInt(8.W)))
val upRegWire = Wire(Vec(32, UInt(8.W)))
val downRegWire = Wire(Vec(16, UInt(8.W)))
val upRegWire = Wire(Vec(16, UInt(8.W)))
@@ -64,7 +64,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
withClockAndReset( io.oser_pclk.asClock, io.reset ){
val downReg = Reg(Vec(32, UInt(8.W))); downRegWire := downReg
val downReg = Reg(Vec(16, UInt(8.W))); downRegWire := downReg
val downCnt = RegInit(0.U(6.W))
@@ -74,7 +74,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( io.reset ){
for( i <- 0 until 32 ){
for( i <- 0 until 16 ){
downReg(i) := 0.U
}
} .otherwise{
@@ -85,7 +85,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( downTimeout ){
downTimeoutEn := false.B
} .elsewhen( downCnt === 32.U ){
} .elsewhen( downCnt === 16.U ){
downTimeoutEn := false.B
} .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
downTimeoutEn := true.B
@@ -93,7 +93,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( downTimeout ){
downCnt := 0.U
}.elsewhen( downCnt === 32.U ){
}.elsewhen( downCnt === 16.U ){
downCnt := 0.U
}.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
downCnt := downCnt + 1.U
@@ -116,13 +116,6 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
// upstream_tx_data_ready := upRegWire(upCnt)
// }
when( io.reset ){
for( i <- 0 until 32 ){
upRegWire(i) := 0.U
}
} .otherwise{
}
when( upTimeout ){
upTimeoutEn := false.B