143 lines
3.7 KiB
Scala
143 lines
3.7 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class BackBoardSlvIO extends Bundle{
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val reset = Input(Bool())
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val oser_pclk = Input(Bool())
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val oser_fclk = Input(Bool())
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val ides_pclk = Input(Bool())
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val ides_fclk = Input(Bool())
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val lvds_down_din = Input(Bool())
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val lvds_down_dout = Output(Bool())
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val lvds_up_din = Input(Bool())
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val lvds_up_dout = Output(Bool())
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}
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abstract class BackBoardSlvBase extends RawModule{
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val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
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val lvdsSlv = Module(new Lvds_Bus_Slave)
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lvdsSlv.io.rst_n := ~io.reset
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lvdsSlv.io.oser_pclk := io.oser_pclk
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lvdsSlv.io.oser_fclk := io.oser_fclk
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lvdsSlv.io.ides_pclk := io.ides_pclk
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lvdsSlv.io.ides_fclk := io.ides_fclk
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lvdsSlv.io.lvds_down_din := io.lvds_down_din
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io.lvds_down_dout := lvdsSlv.io.lvds_down_dout
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lvdsSlv.io.lvds_up_din := io.lvds_up_din
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io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
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val downRegWire = Wire(Vec(16, UInt(8.W)))
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val upRegWire = Wire(Vec(16, UInt(8.W)))
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// val downstream_rx_data_valid = Output(Bool())
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// val downstream_rx_data_out = Output(UInt(8.W))
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// val downstream_rx_crc_valid = Output(Bool())
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// val downstream_rx_crc_err = Output(Bool())
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// val downstream_rx_crc_err_counter = Output(UInt(8.W))
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// val downstream_rx_cdr_err = Output(Bool())
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// val downstream_sync = Output(Bool())
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// val upstream_tx_data_ready = Output(Bool())
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// val upstream_tx_data_in = Input(UInt(8.W))
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// val upstream_rx_crc_valid = Output(Bool())
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// val upstream_rx_crc_err = Output(Bool())
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// val upstream_rx_crc_err_counter = Output(UInt(8.W))
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// val upstream_rx_cdr_err = Output(Bool())
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}
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trait BackBoardSlvDown{ this: BackBoardSlvBase =>
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withClockAndReset( io.oser_pclk.asClock, io.reset ){
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val downReg = Reg(Vec(16, UInt(8.W))); downRegWire := downReg
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val downCnt = RegInit(0.U(6.W))
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val downTimeoutEn = RegInit( false.B )
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val downTimeoutRst = (downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid)
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val ( _, downTimeout ) = Counter( Range( 0,1023 ), downTimeoutEn, downTimeoutRst )
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when( io.reset ){
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for( i <- 0 until 16 ){
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downReg(i) := 0.U
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}
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} .otherwise{
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when( lvdsSlv.io.downstream_rx_data_valid ){
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downReg(downCnt) := lvdsSlv.io.downstream_rx_data_out
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}
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}
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when( downTimeout ){
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downTimeoutEn := false.B
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} .elsewhen( downCnt === 16.U ){
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downTimeoutEn := false.B
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} .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
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downTimeoutEn := true.B
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}
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when( downTimeout ){
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downCnt := 0.U
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}.elsewhen( downCnt === 16.U ){
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downCnt := 0.U
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}.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
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downCnt := downCnt + 1.U
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}
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}
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}
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trait BackBoardSlvUp{ this: BackBoardSlvBase =>
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withClockAndReset( io.oser_pclk.asClock, io.reset ){
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val upCnt = RegInit(31.U(6.W))
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val upTimeoutEn = RegInit( false.B )
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val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
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val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
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lvdsSlv.io.upstream_tx_data_in := upRegWire(upCnt)
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// when( upstream_tx_data_ready ){
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// upstream_tx_data_ready := upRegWire(upCnt)
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// }
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when( upTimeout ){
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upTimeoutEn := false.B
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} .elsewhen( upCnt === 31.U ){
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upTimeoutEn := false.B
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} .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
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upTimeoutEn := true.B
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}
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when( upTimeout ){
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upCnt := 0.U
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}.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
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when(upCnt === 31.U){
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upCnt := 0.U
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} .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
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upCnt := upCnt + 1.U
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}
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}
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}
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}
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