ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

16bit fsmc data; 16*2 reg, 100us

Browse Source
This commit is contained in:
RuigeLee
2023-09-08 16:37:31 +08:00
parent 145db92202
commit bf835014bc
4 changed files with 160 additions and 107 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -8,9 +8,9 @@ import chisel3.util._
class FSMC_Port_Bundle extends Bundle{
val addr = Input(UInt(13.W))
val dataIn = Input(UInt(8.W))
val dataOut = Output(UInt(8.W))
val addr = Input(UInt(11.W))
val dataIn = Input(UInt(16.W))
val dataOut = Output(UInt(16.W))
val dataOEn = Output(Bool())
val cen = Input(Bool())
val oen = Input(Bool())
@@ -38,10 +38,10 @@ class BackBoardMstBase extends RawModule{
val lvdsMst = Module(new Lvds_Bus_Master)
val mirrorDown = Module(new MirrorSRAM(8, 2048))
val mirrorUp = Module(new MirrorSRAM(8, 2048))
val mirrorDown = Module(new MirrorSRAMDown())
val mirrorUp = Module(new MirrorSRAMUp())
val status = Wire(UInt(8.W))
val status = Wire(UInt(16.W))
val slvNum = Wire(UInt(5.W))
@@ -59,7 +59,7 @@ class BackBoardMstBase extends RawModule{
trait BackBoardMstFSMC{ this: BackBoardMstBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val statusReg = RegInit(0.U(8.W)); status := statusReg
val statusReg = RegInit(0.U(16.W)); status := statusReg
val slvNumReg = RegInit(1.U(5.W)); slvNum := slvNumReg
val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
@@ -71,33 +71,35 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
io.FSMC.dataOEn := io.FSMC.oen
val isWriteSRAM = ~fsmcAddrSync.extract(10) & fsmcAddrSync.extract(9)
val isReadSRAM = ~fsmcAddrSync.extract(10) & ~fsmcAddrSync.extract(9)
val isAccessReg = fsmcAddrSync.extract(10)
val activeAddr = fsmcAddrSync(8,0)
val regOut = Wire(UInt(16.W))
mirrorDown.io.enw := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
mirrorDown.io.addrw := fsmcAddrSync(10,0)
mirrorDown.io.dataw := fsmcdataInSync
mirrorDown.io.enw := (~fsmcCEnSync & isWriteSRAM & (~fsmcWEnSync) )
mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := fsmcdataInSync
mirrorUp.io.enr := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
mirrorUp.io.addrr := fsmcAddrSync(10,0)
val regOut = Wire(UInt(8.W))
mirrorUp.io.enr := (~fsmcCEnSync & isReadSRAM & (~fsmcOEnSync) )
mirrorUp.io.addrr := activeAddr
io.FSMC.dataOut := Mux( fsmcAddrSync.extract(12), regOut, mirrorUp.io.datar)
io.FSMC.dataOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
regOut := Mux1H(Seq(
(fsmcAddrSync(10,0) === 0.U) -> status,
(fsmcAddrSync(10,0) === 1.U) -> slvNum,
( activeAddr === 0.U) -> status,
( activeAddr === 1.U) -> slvNum,
))
when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 0.U) ){
when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 0.U) ){
statusReg := fsmcdataInSync
}
when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 1.U) ){
when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 1.U) ){
slvNumReg := fsmcdataInSync
}
@@ -128,7 +130,7 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
stateCur_wire := stateCur
val ( _, trigger ) = Counter(Range( 0,2000) )
val ( _, trigger ) = Counter(Range( 0,1000) )
trigger_wire := trigger
val isSync = RegInit(false.B)
@@ -165,7 +167,7 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
frame_info_update_en := true.B
slave_type_num := Mux(isSync, Cat( "b000".U(3.W), slvNum ), Cat( "b100".U(3.W), slvNum ) )
slave_data_length := (8/8*4*8-1).U
slave_data_length := ((8/8)*16-1).U
tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start
@@ -196,8 +198,8 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
val addrr = RegInit(0.U(11.W))
val addrw = RegInit(0.U(11.W))
val addrr = RegInit(0.U(10.W))
val addrw = RegInit(0.U(10.W))
when( trigger_wire ){
addrw := 0.U
@@ -219,8 +221,6 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
mirrorUp.io.enw := lvdsMst.io.rx_data_valid & ~isSync
mirrorUp.io.dataw := lvdsMst.io.rx_data_out
mirrorUp.io.addrw := addrw
}

19
src/main/scala/backBoard/BackBoardSlv.scala
View File

@@ -36,8 +36,8 @@ abstract class BackBoardSlvBase extends RawModule{
lvdsSlv.io.lvds_up_din := io.lvds_up_din
io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
val downRegWire = Wire(Vec(32, UInt(8.W)))
val upRegWire = Wire(Vec(32, UInt(8.W)))
val downRegWire = Wire(Vec(16, UInt(8.W)))
val upRegWire = Wire(Vec(16, UInt(8.W)))
@@ -64,7 +64,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
withClockAndReset( io.oser_pclk.asClock, io.reset ){
val downReg = Reg(Vec(32, UInt(8.W))); downRegWire := downReg
val downReg = Reg(Vec(16, UInt(8.W))); downRegWire := downReg
val downCnt = RegInit(0.U(6.W))
@@ -74,7 +74,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( io.reset ){
for( i <- 0 until 32 ){
for( i <- 0 until 16 ){
downReg(i) := 0.U
}
} .otherwise{
@@ -85,7 +85,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( downTimeout ){
downTimeoutEn := false.B
} .elsewhen( downCnt === 32.U ){
} .elsewhen( downCnt === 16.U ){
downTimeoutEn := false.B
} .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
downTimeoutEn := true.B
@@ -93,7 +93,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( downTimeout ){
downCnt := 0.U
}.elsewhen( downCnt === 32.U ){
}.elsewhen( downCnt === 16.U ){
downCnt := 0.U
}.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
downCnt := downCnt + 1.U
@@ -116,13 +116,6 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
// upstream_tx_data_ready := upRegWire(upCnt)
// }
when( io.reset ){
for( i <- 0 until 32 ){
upRegWire(i) := 0.U
}
} .otherwise{
}
when( upTimeout ){
upTimeoutEn := false.B

2
src/main/scala/backBoard/LocalRegisters.scala
View File

@@ -11,7 +11,7 @@ class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with
withClockAndReset( io.ides_pclk.asClock, io.reset ){
// val upReg = Reg(Vec(32, UInt(8.W)))
val upReg = RegInit(VecInit((0 until 32).map{i => i.U(8.W)}))
val upReg = RegInit(VecInit((0 until 16).map{i => i.U(8.W)}))
upRegWire := upReg
out := Cat( (0 until 4).map{i => downRegWire(i)}.reverse )
oe := Cat( (4 until 8).map{i => downRegWire(i)}.reverse )

190
src/main/scala/backBoard/MirrorSRAM.scala
View File

@@ -123,73 +123,133 @@ class MirrorSRAM(dw: Int, cl: Int) extends BlackBox with HasBlackBoxInline {
class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
class MirrorSRAMDownIO extends Bundle{
val addrr = Input(UInt(10.W))
val addrw = Input(UInt(9.W))
val dataw = Input( UInt(16.W) )
val datar = Output( UInt(8.W) )
val enw = Input(Bool())
val enr = Input(Bool())
val clockr = Input(Bool())
val clockw = Input(Bool())
}
val io: MirrorSRAMDownIO = IO(new MirrorSRAMDownIO)
setInline("MirrorSRAMDown.v",
"""
| module MirrorSRAMDown(
| input [15:0] dataw,
| input [8:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [9:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [15:0] ram[0:511];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| ram[addrw] <= #1 dataw;
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 addrr[0] ? ram[addrr[9:1]][15:8] : ram[addrr[9:1]][7:0];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 512; i = i + 1 ) begin
| ram[i] = $random;
| end
|
| data_r_reg = $random;
| end
|
|endmodule
""".stripMargin)
}
class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
class MirrorSRAMUpIO extends Bundle{
val addrr = Input(UInt(9.W))
val addrw = Input(UInt(10.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(16.W) )
val enw = Input(Bool())
val enr = Input(Bool())
val clockr = Input(Bool())
val clockw = Input(Bool())
}
val io: MirrorSRAMUpIO = IO(new MirrorSRAMUpIO)
setInline("MirrorSRAMUp.v",
"""
| module MirrorSRAMUp(
| input [7:0] dataw,
| input [9:0] addrw,
| input enw,
|
| output [15:0] datar,
| input [8:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [15:0] ram[0:511];
| reg [15:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| if( addrw[0] ) begin
| ram[addrw[9:1]] <= #1 { dataw, ram[addrw[9:1]][7:0] };
| end else begin
| ram[addrw[9:1]] <= #1 { ram[addrw[9:1]][15:8], dataw };
| end
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 ram[addrr];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 512; i = i + 1 ) begin
| ram[i] = $random;
| end
|
| data_r_reg = $random;
| end
|
|endmodule
""".stripMargin)
}
// class MirrorSRAMIO extends Bundle{
// val datar = Output(UInt(8.W))
// val dataw = Input(UInt(8.W))
// val clock = Input(Bool())
// val reset = Input(Bool())
// val we = Input(Bool())
// val addrr = Input(UInt(11.W))
// val addrw = Input(UInt(11.W))
// }
// class MirrorSRAM extends BlackBox with HasBlackBoxInline {
// val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
// setInline("microSRAM.v",
// """
// | module MirrorSRAM(
// | output [7:0] datar,
// | input [7:0] dataw,
// |
// | input clock,
// | input reset,
// |
// | input we,
// |
// | input [11:0] addrw,
// | input [11:0] addrr
// |
// | );
// |
// | wire [31:0] dout;
// | assign datar = dout[7:0];
// |
// |
// |SDPB bram_sdpb_0 (
// | .DO({dout[31:8],dout[7:0]}),
// | .CLKA(clock),
// | .CEA(we),
// | .RESETA(reset),
// | .CLKB(clock),
// | .CEB(1'b1),
// | .RESETB(reset),
// | .OCE(1'b1),
// | .BLKSELA(3'b0),
// | .BLKSELB(3'b0),
// | .ADA({addrw,3'b0}),
// | .DI({24'b0, dataw}),
// | .ADB({addrr,3'b0})
// | );
// | defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
// | defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
// | defparam bram_sdpb_0.RESET_MODE = "SYNC";
// |
// |endmodule
// """.stripMargin)
// }