rx 通道基本完成32转8，存在跨时钟域风险
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RuigeLee
@@ -6,8 +6,11 @@ import chisel3.util._
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class MacTileLinkRxIO extends Bundle{
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val RxDataLatched2 = Output(UInt(32.W))
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val WriteRxDataToFifo = Output(Bool())
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// val RxDataLatched2 = Output(UInt(8.W))
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// val WriteRxDataToFifo = Output(Bool())
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val asyncToBuf = Decoupled(UInt(8.W))
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val RxAbortLatched = Output(Bool())
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val LatchedRxLength = Output(UInt(16.W))
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val RxStatusInLatched = Output( UInt(9.W) )
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@@ -18,7 +21,7 @@ class MacTileLinkRxIO extends Bundle{
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val RxStatusIn = Input(UInt(9.W))
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val ShiftEndedSyncb = Input(Bool())
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val RxAbortSyncb = Input(Bool())
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val WriteRxDataToFifoSyncb = Input(Bool())
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// val WriteRxDataToFifoSyncb = Input(Bool())
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val Busy_IRQ_rck = Output(Bool())
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val Busy_IRQ_syncb = Input(Bool())
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@@ -35,13 +38,8 @@ class MacTileLinkRxIO extends Bundle{
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class MacTileLinkRx extends Module with RequireAsyncReset{
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val io = IO(new MacTileLinkRxIO)
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val RxDataLatched2 = RegInit(0.U(32.W)); io.RxDataLatched2 := RxDataLatched2
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val RxDataLatched1 = RegInit(0.U(24.W)) // Little Endian Byte Ordering[23:0]
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val RxValidBytes = RegInit(1.U(2.W))
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val RxByteCnt = RegInit(0.U(2.W))
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val LastByteIn = RegInit(false.B)
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val ShiftWillEnd = RegInit(false.B)
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val WriteRxDataToFifo = RegInit(false.B); io.WriteRxDataToFifo := WriteRxDataToFifo
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val RxAbortLatched = RegInit(false.B); io.RxAbortLatched := RxAbortLatched
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val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength
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@@ -53,77 +51,21 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
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val Busy_IRQ_rck = RegInit(false.B); io.Busy_IRQ_rck := Busy_IRQ_rck
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// Indicating that last byte is being reveived
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when(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){
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LastByteIn := false.B
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} .elsewhen(io.RxValid & io.RxReady & io.RxEndFrm & ~(RxByteCnt.andR) & RxEnableWindow){
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LastByteIn := true.B
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}
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// Indicating that data reception will end
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val StartShiftWillEnd = LastByteIn | io.RxValid & io.RxEndFrm & RxByteCnt.andR & RxEnableWindow
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when(ShiftEnded_rck | io.RxAbort){
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ShiftWillEnd := false.B
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} .elsewhen(StartShiftWillEnd){
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ShiftWillEnd := true.B
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}
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// Receive byte counter
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when(ShiftEnded_rck | io.RxAbort){
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RxByteCnt := 0.U
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} .elsewhen(io.RxValid & io.RxStartFrm & io.RxReady){
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RxByteCnt := 1.U
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} .elsewhen(io.RxValid & RxEnableWindow & io.RxReady | LastByteIn){
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RxByteCnt := RxByteCnt + 1.U
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}
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// Indicates how many bytes are valid within the last word
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when(io.RxValid & io.RxStartFrm){
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RxValidBytes := 1.U
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} .elsewhen(io.RxValid & ~LastByteIn & ~io.RxStartFrm & RxEnableWindow){
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RxValidBytes := RxValidBytes + 1.U
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}
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when(io.RxValid & io.RxReady & ~LastByteIn){
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when(io.RxStartFrm){
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RxDataLatched1 := Cat(RxDataLatched1(23, 8), io.RxData)// Little Endian Byte Ordering
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} .elsewhen(RxEnableWindow){
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RxDataLatched1 := Mux1H(Seq(
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( RxByteCnt === 0.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),// Little Endian Byte Ordering
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( RxByteCnt === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)),
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( RxByteCnt === 2.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),
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( RxByteCnt === 3.U ) -> RxDataLatched1,
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))
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}
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}
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// Indicating start of the reception process
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val SetWriteRxDataToFifo =
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(io.RxValid & io.RxReady & ~io.RxStartFrm & RxEnableWindow & (RxByteCnt.andR)) |
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(ShiftWillEnd & LastByteIn & (RxByteCnt.andR))
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io.RxValid & io.RxReady & (io.RxStartFrm | RxEnableWindow )
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// Assembling data that will be written to the rx_fifo
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when(SetWriteRxDataToFifo & ~ShiftWillEnd){
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RxDataLatched2 := Cat(io.RxData, RxDataLatched1)// Little Endian Byte Ordering
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} .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){
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RxDataLatched2 := Mux1H(Seq( // Little Endian Byte Ordering
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( RxValidBytes === 0.U ) -> Cat(io.RxData, RxDataLatched1),
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( RxValidBytes === 1.U ) -> Cat(0.U(24.W), RxDataLatched1(7,0) ),
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( RxValidBytes === 2.U ) -> Cat(0.U(16.W), RxDataLatched1(15, 0) ),
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( RxValidBytes === 3.U ) -> Cat(0.U(8.W), RxDataLatched1 ),
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))
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}
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when(SetWriteRxDataToFifo & ~io.RxAbort){
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WriteRxDataToFifo := true.B
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} .elsewhen(io.WriteRxDataToFifoSyncb | io.RxAbort){
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WriteRxDataToFifo := false.B
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}
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// when(SetWriteRxDataToFifo & ~io.RxAbort){
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// WriteRxDataToFifo := true.B
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// RxDataLatched2 := io.RxData
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// } .elsewhen(io.WriteRxDataToFifoSyncb | io.RxAbort){
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// WriteRxDataToFifo := false.B
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// }
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// Generation of the end-of-frame signal
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when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){
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when(SetWriteRxDataToFifo & ~io.RxAbort & io.RxEndFrm){
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ShiftEnded_rck := true.B
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} .elsewhen(io.RxAbort | io.ShiftEndedSyncb & RegNext(io.ShiftEndedSyncb, false.B) ){
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ShiftEnded_rck := false.B
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@@ -150,6 +92,12 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
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}
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val rxFifo = Module(new Queue(UInt(8.W), 4))
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rxFifo.io.enq.valid := SetWriteRxDataToFifo & ~io.RxAbort
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rxFifo.io.enq.bits := io.RxData
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assert( ~(rxFifo.io.enq.valid & ~rxFifo.io.enq.ready) )
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io.asyncToBuf <> rxFifo.io.deq
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}
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