From bf66bae4754ee20d3fdf01d341a891bde3448f8f Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Sat, 21 Oct 2023 21:08:40 +0800 Subject: [PATCH] =?UTF-8?q?rx=20=E9=80=9A=E9=81=93=E5=9F=BA=E6=9C=AC?= =?UTF-8?q?=E5=AE=8C=E6=88=9032=E8=BD=AC8=EF=BC=8C=E5=AD=98=E5=9C=A8?= =?UTF-8?q?=E8=B7=A8=E6=97=B6=E9=92=9F=E5=9F=9F=E9=A3=8E=E9=99=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/Switch/RxBuff.scala | 20 ++-- src/main/scala/Switch/SwitchMux.scala | 12 +-- src/main/scala/Switch/TxBuff.scala | 6 +- src/main/scala/Switch/WithSwitch.scala | 12 +-- src/main/scala/Switch/mac/MAC.scala | 26 ++--- src/main/scala/Switch/mac/MacTileLinkRx.scala | 96 +++++-------------- src/main/scala/Switch/mac/MacTileLinkTx.scala | 48 ++-------- src/main/scala/Switch/mac/MacTilelink.scala | 38 +++----- 8 files changed, 79 insertions(+), 179 deletions(-) diff --git a/src/main/scala/Switch/RxBuff.scala b/src/main/scala/Switch/RxBuff.scala index 3374121..7bd48b9 100644 --- a/src/main/scala/Switch/RxBuff.scala +++ b/src/main/scala/Switch/RxBuff.scala @@ -14,15 +14,15 @@ class Receive_Deq_Ctrl_Bundle extends Receive_Enq_Ctrl_Bundle{ } class Receive_Enq_Bundle extends Bundle{ - val data = Decoupled(UInt(32.W)) + val data = Decoupled(UInt(8.W)) val ctrl = Decoupled(new Receive_Enq_Ctrl_Bundle) } class Receive_Deq_Bundle extends Bundle{ - val data = Decoupled(UInt(32.W)) + val data = Decoupled(UInt(8.W)) val ctrl = Decoupled(new Receive_Deq_Ctrl_Bundle) - val header = Decoupled(Vec( 5, UInt(32.W) ) ) + val header = Decoupled(Vec( 20, UInt(8.W) ) ) } @@ -49,20 +49,20 @@ class RxBuffBase extends Module{ val isDeqPo = ~isEnqPi - val buff = for( i <- 0 until 2 ) yield { Module(new Queue( UInt(32.W), 2048/4 )) } + val buff = for( i <- 0 until 2 ) yield { Module(new Queue( UInt(8.W), 2048 )) } val info = for( i <- 0 until 2 ) yield { Reg(new Receive_Enq_Ctrl_Bundle) } // dontTouch(buff(0).io.enq) // dontTouch(info(0)) // dontTouch(buff(1).io.enq) // dontTouch(info(1)) - val header = for( i <- 0 until 2 ) yield { Reg(Vec( 5, UInt(32.W) )) } + val header = for( i <- 0 until 2 ) yield { Reg(Vec( 20, UInt(8.W) )) } val hValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } val cValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val recCnt = RegInit(0.U(3.W)) + val recCnt = RegInit(0.U(5.W)) } @@ -98,7 +98,7 @@ trait RxBuffEnq{ this: RxBuffBase => when( io.enq.ctrl.fire ){ recCnt := 0.U } .elsewhen( io.enq.data.fire ){ - when( recCnt < 5.U ){ + when( recCnt < 20.U ){ recCnt := recCnt + 1.U when( isEnqPi ){ header(0)(recCnt) := io.enq.data.bits @@ -107,8 +107,8 @@ trait RxBuffEnq{ this: RxBuffBase => } .otherwise{ assert(false.B, "Assert Failed, Rx Under Run") } - }.elsewhen( recCnt === 5.U ){ - recCnt := 6.U + }.elsewhen( recCnt === 20.U ){ + recCnt := 21.U } } @@ -119,7 +119,7 @@ trait RxBuffDeq{ this: RxBuffBase => when( io.deq.header.fire ){ when( isDeqPi ) { hValid(0) := false.B } when( isDeqPo ) { hValid(1) := false.B } - } .elsewhen( io.enq.data.fire & recCnt === 5.U ){ + } .elsewhen( io.enq.data.fire & recCnt === 20.U ){ when( isEnqPi ) { hValid(0) := true.B } when( isEnqPo ) { hValid(1) := true.B } } diff --git a/src/main/scala/Switch/SwitchMux.scala b/src/main/scala/Switch/SwitchMux.scala index b924333..4a3b562 100644 --- a/src/main/scala/Switch/SwitchMux.scala +++ b/src/main/scala/Switch/SwitchMux.scala @@ -96,7 +96,7 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule when( stateCur === stateIdle ){ dmaAddress := ptr } .elsewhen( io.dmaMst.A.fire ){ - dmaAddress := dmaAddress + 4.U + dmaAddress := dmaAddress + 1.U } rxBuff.io.deq.data.ready := io.dmaMst.A.fire & (stateCur === stateRx) @@ -111,18 +111,18 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule dmaTxABits := edgeOut.Get( fromSource = 0.U, - toAddress = dmaAddress >> 2 << 2, - lgSize = log2Ceil(32/8).U, + toAddress = dmaAddress, + lgSize = log2Ceil(8/8).U, )._2 } .elsewhen( rxBuff.io.deq.header.fire | (stateCur === stateRx & io.dmaMst.D.fire & isLastD & rxBuff.io.deq.data.valid ) ) { dmaTxAValid := true.B dmaTxABits := edgeOut.Put( fromSource = 0.U, - toAddress = dmaAddress >> 2 << 2, - lgSize = log2Ceil(32/8).U, + toAddress = dmaAddress, + lgSize = log2Ceil(8/8).U, data = rxBuff.io.deq.data.bits, - mask = "b1111".U, + mask = "b1".U, )._2 } diff --git a/src/main/scala/Switch/TxBuff.scala b/src/main/scala/Switch/TxBuff.scala index e66cef1..f737bc7 100644 --- a/src/main/scala/Switch/TxBuff.scala +++ b/src/main/scala/Switch/TxBuff.scala @@ -24,7 +24,7 @@ class Transmit_Resp_Bundle extends Bundle{ } class Transmit_Bundle extends Bundle{ - val data = Decoupled(UInt(32.W)) + val data = Decoupled(UInt(8.W)) val req = Decoupled(new Transmit_Req_Bundle) val resp = Flipped(Decoupled(new Transmit_Resp_Bundle)) } @@ -40,7 +40,7 @@ abstract class TxBuffBase extends Module{ - val buff = Module(new Queue( UInt(32.W), 2048/4 )) + val buff = Module(new Queue( UInt(8.W), 2048 )) val reqInfo = Reg(new Transmit_Req_Bundle) val respInfo = Reg(new Transmit_Resp_Bundle) val enqCnt = Reg(UInt(16.W)) @@ -60,7 +60,7 @@ trait TxBuffEnq{ this: TxBuffBase => enqCnt := 0.U reqInfo := io.enq.req.bits } .elsewhen( io.enq.data.fire ){ - enqCnt := enqCnt + 4.U + enqCnt := enqCnt + 1.U // when( enqCnt + 4.U >= reqInfo.txLength ){ // } } diff --git a/src/main/scala/Switch/WithSwitch.scala b/src/main/scala/Switch/WithSwitch.scala index 6cd0272..c9fc6b0 100644 --- a/src/main/scala/Switch/WithSwitch.scala +++ b/src/main/scala/Switch/WithSwitch.scala @@ -12,7 +12,7 @@ trait WithSwitchMix { this: BaseSubsystem => val switch = LazyModule(new Switch) - sbus.coupleFrom("switch_mst") { _ := TLBuffer() := switch.tlClientNode } + sbus.coupleFrom("switch_mst") { _ := TLBuffer() := TLWidthWidget(8 / 8) := switch.tlClientNode } // pbus.coupleTo("switch_cfg") { switch0.tlMasterNode := TLFragmenter(pbus) := _ } pbus.coupleTo("switch_cfg") { switch.ethReg.configNode := TLFragmenter(pbus) := _ } @@ -28,11 +28,11 @@ trait WithSwitchMixModuleImp extends LazyModuleImp { switchIO <> outer.switch.module.io - println("Warning, did you delete the rocket-chip.jar on top to reflash?") - println("Warning, did you delete the rocket-chip.jar on top to reflash?") - println("Warning, did you delete the rocket-chip.jar on top to reflash?") - println("Warning, did you delete the rocket-chip.jar on top to reflash?") - println("Warning, did you delete the rocket-chip.jar on top to reflash?") + // println("Warning, did you delete the rocket-chip.jar on top to reflash?") + // println("Warning, did you delete the rocket-chip.jar on top to reflash?") + // println("Warning, did you delete the rocket-chip.jar on top to reflash?") + // println("Warning, did you delete the rocket-chip.jar on top to reflash?") + // println("Warning, did you delete the rocket-chip.jar on top to reflash?") } diff --git a/src/main/scala/Switch/mac/MAC.scala b/src/main/scala/Switch/mac/MAC.scala index 3eebc96..fe002ec 100644 --- a/src/main/scala/Switch/mac/MAC.scala +++ b/src/main/scala/Switch/mac/MAC.scala @@ -5,7 +5,7 @@ import chisel3.util._ import Switch._ - +import freechips.rocketchip.util._ class MII extends Bundle with MDIO{ // Tx @@ -756,7 +756,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb - macTileLinkTx.io.TxValidBytesLatched := wishbone.io.TxValidBytesLatched macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb wishbone.io.TxUsedData := TxUsedData @@ -795,10 +794,8 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M - wishbone.io.RxDataLatched2_rxclk := macTileLinkRx.io.RxDataLatched2 - val WriteRxDataToFifoSync = ShiftRegister(macTileLinkRx.io.WriteRxDataToFifo, 2, false.B, true.B) - wishbone.io.WriteRxDataToFifoSync := WriteRxDataToFifoSync + val RxAbortSync = ShiftRegister( macTileLinkRx.io.RxAbortLatched, 2, false.B, true.B ) wishbone.io.RxAbortSync := RxAbortSync @@ -807,11 +804,18 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M wishbone.io.ShiftEndedSync := ShiftEndedSync + val req_ToAsync = Wire(new AsyncBundle(UInt(8.W))) + + + wishbone.io.syncToBuf <> FromAsyncBundle( req_ToAsync ) + + withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset) { + req_ToAsync <> ToAsyncBundle( macTileLinkRx.io.asyncToBuf ) + } - - wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength - wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched + wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength + wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched @@ -820,14 +824,14 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B) withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) { - val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 2, false.B, true.B) + val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 3, false.B, true.B) //async 3 cycle for protect wishbone.io.syncToBuf.valid + println("Warning, No protect in ShiftEndedSyncb?!") RxStatusWriteLatchedSync := ShiftEndedSyncb macTileLinkRx.io.ShiftEndedSyncb := ShiftEndedSyncb macTileLinkRx.io.RxAbortSyncb := ShiftRegister( RxAbortSync, 2, false.B, true.B ) macTileLinkRx.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B ) - macTileLinkRx.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync, 2, false.B, true.B ) - macTileLinkRx.io.RxReady := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B ) + macTileLinkRx.io.RxReady := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B ) } macTileLinkRx.io.RxData := RxData diff --git a/src/main/scala/Switch/mac/MacTileLinkRx.scala b/src/main/scala/Switch/mac/MacTileLinkRx.scala index 52390e9..d0e3b4b 100644 --- a/src/main/scala/Switch/mac/MacTileLinkRx.scala +++ b/src/main/scala/Switch/mac/MacTileLinkRx.scala @@ -6,8 +6,11 @@ import chisel3.util._ class MacTileLinkRxIO extends Bundle{ - val RxDataLatched2 = Output(UInt(32.W)) - val WriteRxDataToFifo = Output(Bool()) + // val RxDataLatched2 = Output(UInt(8.W)) + // val WriteRxDataToFifo = Output(Bool()) + + val asyncToBuf = Decoupled(UInt(8.W)) + val RxAbortLatched = Output(Bool()) val LatchedRxLength = Output(UInt(16.W)) val RxStatusInLatched = Output( UInt(9.W) ) @@ -18,7 +21,7 @@ class MacTileLinkRxIO extends Bundle{ val RxStatusIn = Input(UInt(9.W)) val ShiftEndedSyncb = Input(Bool()) val RxAbortSyncb = Input(Bool()) - val WriteRxDataToFifoSyncb = Input(Bool()) + // val WriteRxDataToFifoSyncb = Input(Bool()) val Busy_IRQ_rck = Output(Bool()) val Busy_IRQ_syncb = Input(Bool()) @@ -35,13 +38,8 @@ class MacTileLinkRxIO extends Bundle{ class MacTileLinkRx extends Module with RequireAsyncReset{ val io = IO(new MacTileLinkRxIO) - val RxDataLatched2 = RegInit(0.U(32.W)); io.RxDataLatched2 := RxDataLatched2 - val RxDataLatched1 = RegInit(0.U(24.W)) // Little Endian Byte Ordering[23:0] - val RxValidBytes = RegInit(1.U(2.W)) - val RxByteCnt = RegInit(0.U(2.W)) - val LastByteIn = RegInit(false.B) + val ShiftWillEnd = RegInit(false.B) - val WriteRxDataToFifo = RegInit(false.B); io.WriteRxDataToFifo := WriteRxDataToFifo val RxAbortLatched = RegInit(false.B); io.RxAbortLatched := RxAbortLatched val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength @@ -53,77 +51,21 @@ class MacTileLinkRx extends Module with RequireAsyncReset{ val Busy_IRQ_rck = RegInit(false.B); io.Busy_IRQ_rck := Busy_IRQ_rck - - - // Indicating that last byte is being reveived - when(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){ - LastByteIn := false.B - } .elsewhen(io.RxValid & io.RxReady & io.RxEndFrm & ~(RxByteCnt.andR) & RxEnableWindow){ - LastByteIn := true.B - } - - // Indicating that data reception will end - val StartShiftWillEnd = LastByteIn | io.RxValid & io.RxEndFrm & RxByteCnt.andR & RxEnableWindow - when(ShiftEnded_rck | io.RxAbort){ - ShiftWillEnd := false.B - } .elsewhen(StartShiftWillEnd){ - ShiftWillEnd := true.B - } - - // Receive byte counter - when(ShiftEnded_rck | io.RxAbort){ - RxByteCnt := 0.U - } .elsewhen(io.RxValid & io.RxStartFrm & io.RxReady){ - RxByteCnt := 1.U - } .elsewhen(io.RxValid & RxEnableWindow & io.RxReady | LastByteIn){ - RxByteCnt := RxByteCnt + 1.U - } - - // Indicates how many bytes are valid within the last word - when(io.RxValid & io.RxStartFrm){ - RxValidBytes := 1.U - } .elsewhen(io.RxValid & ~LastByteIn & ~io.RxStartFrm & RxEnableWindow){ - RxValidBytes := RxValidBytes + 1.U - } - - when(io.RxValid & io.RxReady & ~LastByteIn){ - when(io.RxStartFrm){ - RxDataLatched1 := Cat(RxDataLatched1(23, 8), io.RxData)// Little Endian Byte Ordering - } .elsewhen(RxEnableWindow){ - RxDataLatched1 := Mux1H(Seq( - ( RxByteCnt === 0.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),// Little Endian Byte Ordering - ( RxByteCnt === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)), - ( RxByteCnt === 2.U ) -> Cat( io.RxData, RxDataLatched1(15,0)), - ( RxByteCnt === 3.U ) -> RxDataLatched1, - )) - } - } - // Indicating start of the reception process val SetWriteRxDataToFifo = - (io.RxValid & io.RxReady & ~io.RxStartFrm & RxEnableWindow & (RxByteCnt.andR)) | - (ShiftWillEnd & LastByteIn & (RxByteCnt.andR)) + io.RxValid & io.RxReady & (io.RxStartFrm | RxEnableWindow ) - // Assembling data that will be written to the rx_fifo - when(SetWriteRxDataToFifo & ~ShiftWillEnd){ - RxDataLatched2 := Cat(io.RxData, RxDataLatched1)// Little Endian Byte Ordering - } .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){ - RxDataLatched2 := Mux1H(Seq( // Little Endian Byte Ordering - ( RxValidBytes === 0.U ) -> Cat(io.RxData, RxDataLatched1), - ( RxValidBytes === 1.U ) -> Cat(0.U(24.W), RxDataLatched1(7,0) ), - ( RxValidBytes === 2.U ) -> Cat(0.U(16.W), RxDataLatched1(15, 0) ), - ( RxValidBytes === 3.U ) -> Cat(0.U(8.W), RxDataLatched1 ), - )) - } - when(SetWriteRxDataToFifo & ~io.RxAbort){ - WriteRxDataToFifo := true.B - } .elsewhen(io.WriteRxDataToFifoSyncb | io.RxAbort){ - WriteRxDataToFifo := false.B - } + + // when(SetWriteRxDataToFifo & ~io.RxAbort){ + // WriteRxDataToFifo := true.B + // RxDataLatched2 := io.RxData + // } .elsewhen(io.WriteRxDataToFifoSyncb | io.RxAbort){ + // WriteRxDataToFifo := false.B + // } // Generation of the end-of-frame signal - when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){ + when(SetWriteRxDataToFifo & ~io.RxAbort & io.RxEndFrm){ ShiftEnded_rck := true.B } .elsewhen(io.RxAbort | io.ShiftEndedSyncb & RegNext(io.ShiftEndedSyncb, false.B) ){ ShiftEnded_rck := false.B @@ -150,6 +92,12 @@ class MacTileLinkRx extends Module with RequireAsyncReset{ } + val rxFifo = Module(new Queue(UInt(8.W), 4)) + rxFifo.io.enq.valid := SetWriteRxDataToFifo & ~io.RxAbort + rxFifo.io.enq.bits := io.RxData + assert( ~(rxFifo.io.enq.valid & ~rxFifo.io.enq.ready) ) + + io.asyncToBuf <> rxFifo.io.deq } diff --git a/src/main/scala/Switch/mac/MacTileLinkTx.scala b/src/main/scala/Switch/mac/MacTileLinkTx.scala index 8620ce5..5fcb6c1 100644 --- a/src/main/scala/Switch/mac/MacTileLinkTx.scala +++ b/src/main/scala/Switch/mac/MacTileLinkTx.scala @@ -22,8 +22,7 @@ class MacTileLinkTxIO extends Bundle{ val ReadTxDataFromFifo_syncb = Input(Bool()) val TxEndFrm_wb = Input(Bool()) - val TxValidBytesLatched = Input(UInt(2.W)) - val TxData_wb = Input(UInt(32.W)) + val TxData_wb = Input(UInt(8.W)) } @@ -38,8 +37,6 @@ class MacTileLinkTx extends Module with RequireAsyncReset{ val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm val TxData = RegInit(0.U(8.W)); io.TxData := TxData - val TxDataLatched = RegInit(0.U(32.W)) - val TxByteCnt = RegInit(0.U(2.W)) val LastWord = RegInit(false.B) val ReadTxDataFromFifo_tck = RegInit(false.B); io.ReadTxDataFromFifo_tck := ReadTxDataFromFifo_tck @@ -65,7 +62,7 @@ class MacTileLinkTx extends Module with RequireAsyncReset{ // Indication of the last word when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){ LastWord := false.B - } .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){ + } .elsewhen( io.TxUsedData & Flop ){ LastWord := io.TxEndFrm_wb } @@ -73,50 +70,17 @@ class MacTileLinkTx extends Module with RequireAsyncReset{ when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){ TxEndFrm := false.B } .elsewhen(Flop & LastWord){ - TxEndFrm := - Mux1H(Seq( - (io.TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U), - (io.TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U), - (io.TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U), - (io.TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U), - )) - } - - // Tx data selection (latching) - when( io.TxStartFrm_sync & ~TxStartFrm ){ - TxData := io.TxData_wb( 7, 0) // little Endian Byte Ordering - } .elsewhen(io.TxUsedData & Flop){ - TxData := Mux1H(Seq( - (TxByteCnt === 0.U) -> TxDataLatched( 7, 0),// little Endian Byte Ordering - (TxByteCnt === 1.U) -> TxDataLatched(15, 8), - (TxByteCnt === 2.U) -> TxDataLatched(23,16), - (TxByteCnt === 3.U) -> TxDataLatched(31,24), - )) - } - - // Latching tx data - when( - io.TxStartFrm_sync & ~TxStartFrm | - io.TxUsedData & Flop & TxByteCnt === 3.U | - TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){ - TxDataLatched := io.TxData_wb + TxEndFrm := true.B } - // Tx Byte counter - when(TxAbort_q | TxRetry_q){ - TxByteCnt := 0.U - } .elsewhen(TxStartFrm & ~io.TxUsedData){ - TxByteCnt := 1.U - } .elsewhen(io.TxUsedData & Flop){ - TxByteCnt := TxByteCnt + 1.U - } when( io.TxStartFrm_sync & ~TxStartFrm | - io.TxUsedData & Flop & TxByteCnt === 3.U & ~LastWord | - TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){ + io.TxUsedData & Flop & ~LastWord | + TxStartFrm & io.TxUsedData & Flop ){ ReadTxDataFromFifo_tck := true.B + TxData := io.TxData_wb( 7, 0) } .elsewhen(io.ReadTxDataFromFifo_syncb & ~RegNext(io.ReadTxDataFromFifo_syncb, false.B)){ ReadTxDataFromFifo_tck := false.B } diff --git a/src/main/scala/Switch/mac/MacTilelink.scala b/src/main/scala/Switch/mac/MacTilelink.scala index 9048f4a..26f5ae7 100644 --- a/src/main/scala/Switch/mac/MacTilelink.scala +++ b/src/main/scala/Switch/mac/MacTilelink.scala @@ -20,8 +20,10 @@ abstract class MacTileLinkBase() extends Module{ class MacTileLinkIO extends Bundle{ val r_RxEn = Input(Bool()) // Receive enable - val RxDataLatched2_rxclk = Input(UInt(32.W)) - val WriteRxDataToFifoSync = Input(Bool()) + + val syncToBuf = Flipped(Decoupled(UInt(8.W))) + // val RxDataLatched2_rxclk = Input(UInt(8.W)) + // val WriteRxDataToFifoSync = Input(Bool()) val RxAbortSync = Input(Bool()) val LatchedRxLength_rxclk = Input(UInt(16.W)) val RxStatusInLatched_rxclk = Input(UInt(9.W)) @@ -33,7 +35,7 @@ abstract class MacTileLinkBase() extends Module{ val TxStartFrm_syncb = Input(Bool()) val TxEndFrm_wb = Output(Bool()) - val TxData_wb = Output(UInt(32.W)) + val TxData_wb = Output(UInt(8.W)) val ReadTxDataFromFifo_sync = Input(Bool()) // Tx Status signals @@ -49,7 +51,6 @@ abstract class MacTileLinkBase() extends Module{ val r_TxEn = Input(Bool()) // Transmit enable val BlockingTxStatusWrite = Output(Bool()) val TxUsedData = Input(Bool()) // Transmit packet used data - val TxValidBytesLatched = Output(UInt(2.W)) val TxRetrySync = Input(Bool()) val TxAbortSync = Input(Bool()) // Transmit packet abort @@ -68,9 +69,9 @@ abstract class MacTileLinkBase() extends Module{ - val ShiftEndedSyncPluse = io.ShiftEndedSync & ~RegNext(io.ShiftEndedSync, false.B) + val ShiftEndedSyncPluse = io.ShiftEndedSync & io.syncToBuf.valid & ~RegNext(io.ShiftEndedSync & io.syncToBuf.valid, false.B) val RxAbortPluse = io.RxAbortSync & ~RegNext(io.RxAbortSync, false.B) - val WriteRxDataToFifoSyncPluse = io.WriteRxDataToFifoSync & ~RegNext(io.WriteRxDataToFifoSync, false.B) + // val WriteRxDataToFifoSyncPluse = io.WriteRxDataToFifoSync & ~RegNext(io.WriteRxDataToFifoSync, false.B) val RxReady = RegInit(false.B); io.RxReady := RxReady @@ -97,8 +98,7 @@ abstract class MacTileLinkBase() extends Module{ } - io.rxEnq.data.bits := io.RxDataLatched2_rxclk - io.rxEnq.data.valid := WriteRxDataToFifoSyncPluse + io.rxEnq.data <> io.syncToBuf assert( ~(io.rxEnq.data.valid & ~io.rxEnq.data.ready), "Assert Failed, rx overrun!" ) @@ -144,7 +144,7 @@ abstract class MacTileLinkBase() extends Module{ } - when(((TxLength - 4.U) === 0.U) & io.TxUsedData){ + when(((TxLength - 1.U) === 0.U) & io.TxUsedData){ TxEndFrm_wb := true.B } .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){ TxEndFrm_wb := false.B @@ -155,10 +155,10 @@ abstract class MacTileLinkBase() extends Module{ TxLength := io.txDeq.req.bits.txLength LatchedTxLength := io.txDeq.req.bits.txLength } .elsewhen( io.txDeq.data.fire ){ - when( TxLength < 4.U ){ + when( TxLength < 1.U ){ TxLength := 0.U } .otherwise{ - TxLength := TxLength - 4.U // Length is subtracted at the data request + TxLength := TxLength - 1.U // Length is subtracted at the data request } } @@ -232,22 +232,6 @@ abstract class MacTileLinkBase() extends Module{ - // Marks which bytes are valid within the word. - val TxValidBytesLatched = RegInit(0.U(2.W)); io.TxValidBytesLatched := TxValidBytesLatched - val LatchValidBytes = ShiftRegisters((TxLength < 4.U), 2, false.B, true.B) - val LatchValidBytesPluse = LatchValidBytes(0) & ~LatchValidBytes(1) - - // Latching valid bytes - when(LatchValidBytesPluse){ - TxValidBytesLatched := Mux(TxLength < 4.U, TxLength(1,0), 0.U) - } .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){ - TxValidBytesLatched := 0.U - } - - - - - }