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tl2cdr增加附带io

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This commit is contained in:
Ruige Lee (WSL)
2025-01-16 17:57:44 +08:00
parent e54ddab4e2
commit bf0e345cc9
3 changed files with 21 additions and 1 deletions
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17
src/main/scala/backBoard/ebus/TL2CDR.scala
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@@ -46,6 +46,9 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba
val tld = new DecoupledIO(new TLBundleD(edge.bundle)) val tld = new DecoupledIO(new TLBundleD(edge.bundle))
val interrupt = Output(Vec(4, Bool())) val interrupt = Output(Vec(4, Bool()))
val isOnline = Output(Bool())
val isLast = Input(Bool())
} }
val io: TLCDRIO = IO(new TLCDRIO) val io: TLCDRIO = IO(new TLCDRIO)
@@ -226,7 +229,17 @@ trait TL2CDRRx{ this: TL2CDRBase =>
} }
class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) with TL2CDRTx with TL2CDRRx{ trait TL2CDRIsLast{ this: TL2CDRBase =>
io.isOnline := false.B
val isReadIsLast = io.tla.fire & io.tla.bits.address(5,0) === "h20".U & io.tla.bits.opcode === 4.U
}
class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge)
with TL2CDRTx with TL2CDRRx
with TL2CDRIsLast
{
// val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U // val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
@@ -287,6 +300,8 @@ class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) wi
rdata := rxLen rdata := rxLen
} .elsewhen(isTLReadRxFifo ){ } .elsewhen(isTLReadRxFifo ){
rdata := rxFifo.io.deq.bits rdata := rxFifo.io.deq.bits
} .elsewhen(isReadIsLast){
rdata := io.isLast
} }

3
tb/sw/tl2cdr/tl2cdr.c
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@@ -14,6 +14,9 @@ volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset
volatile uint32_t *cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read volatile uint32_t *cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
volatile uint32_t *cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read volatile uint32_t *cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
volatile uint32_t *cdr_IsLast = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
void cdr_set_downStream(){ void cdr_set_downStream(){
*cdr_softReset = 1; //复位脉冲 *cdr_softReset = 1; //复位脉冲
*cdr_direct = 0; *cdr_direct = 0;

2
tb/sw/tl2cdr/tl2cdr.h
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@@ -22,6 +22,7 @@
#define CDR_WriteSoftReset 0x10 #define CDR_WriteSoftReset 0x10
#define CDR_ReadRxLen 0x18 #define CDR_ReadRxLen 0x18
#define CDR_ReadRxFifo 0x1c #define CDR_ReadRxFifo 0x1c
#define CDR_ReadIsLast 0x20
extern volatile uint32_t *cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read extern volatile uint32_t *cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
extern volatile uint32_t *cdr_txLen = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write extern volatile uint32_t *cdr_txLen = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
@@ -30,6 +31,7 @@ extern volatile uint32_t *cdr_direct = (uint32_t*)( TL2CDR_BASE + CDR_WriteTrans
extern volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write extern volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
extern volatile uint32_t *cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read extern volatile uint32_t *cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
extern volatile uint32_t *cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read extern volatile uint32_t *cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
extern volatile uint32_t *cdr_IsLast = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
// extern uint8_t gpio_read(); // extern uint8_t gpio_read();
// extern uint32_t gpio_write( uint32_t data ); // extern uint32_t gpio_write( uint32_t data );