From bf0e345cc979f4b8afbf8c2e5167912b40a0f2af Mon Sep 17 00:00:00 2001
From: "Ruige Lee (WSL)" <295054118@whut.edu.cn>
Date: Thu, 16 Jan 2025 17:57:44 +0800
Subject: [PATCH] =?UTF-8?q?tl2cdr=E5=A2=9E=E5=8A=A0=E9=99=84=E5=B8=A6io?=
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---
 src/main/scala/backBoard/ebus/TL2CDR.scala | 17 ++++++++++++++++-
 tb/sw/tl2cdr/tl2cdr.c                      |  3 +++
 tb/sw/tl2cdr/tl2cdr.h                      |  2 ++
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/backBoard/ebus/TL2CDR.scala b/src/main/scala/backBoard/ebus/TL2CDR.scala
index 16aac2a..4da4548 100644
--- a/src/main/scala/backBoard/ebus/TL2CDR.scala
+++ b/src/main/scala/backBoard/ebus/TL2CDR.scala
@@ -46,6 +46,9 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba
     val tld = new DecoupledIO(new TLBundleD(edge.bundle))
 
     val interrupt = Output(Vec(4, Bool()))
+
+    val isOnline = Output(Bool())
+    val isLast   = Input(Bool())
   }
 
   val io: TLCDRIO = IO(new TLCDRIO)
@@ -226,7 +229,17 @@ trait TL2CDRRx{ this: TL2CDRBase =>
 
 }
 
-class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) with TL2CDRTx with TL2CDRRx{
+trait TL2CDRIsLast{ this: TL2CDRBase =>
+  io.isOnline := false.B
+  val isReadIsLast = io.tla.fire & io.tla.bits.address(5,0) === "h20".U & io.tla.bits.opcode === 4.U
+
+}
+
+
+class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge)
+with TL2CDRTx with TL2CDRRx
+with TL2CDRIsLast
+{
 
   // val isWriteTransDir       = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
   val isWriteTransDir       = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
@@ -287,6 +300,8 @@ class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) wi
     rdata := rxLen
   } .elsewhen(isTLReadRxFifo      ){
     rdata := rxFifo.io.deq.bits
+  } .elsewhen(isReadIsLast){
+    rdata := io.isLast
   }
 
 
diff --git a/tb/sw/tl2cdr/tl2cdr.c b/tb/sw/tl2cdr/tl2cdr.c
index ac7db2d..f970087 100644
--- a/tb/sw/tl2cdr/tl2cdr.c
+++ b/tb/sw/tl2cdr/tl2cdr.c
@@ -14,6 +14,9 @@ volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset
 volatile uint32_t *cdr_rxLen     = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
 volatile uint32_t *cdr_rxFifo    = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
 
+volatile uint32_t *cdr_IsLast    = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
+
+
 void cdr_set_downStream(){
 	*cdr_softReset = 1; //复位脉冲
 	*cdr_direct = 0;
diff --git a/tb/sw/tl2cdr/tl2cdr.h b/tb/sw/tl2cdr/tl2cdr.h
index 1b9240f..eacf777 100644
--- a/tb/sw/tl2cdr/tl2cdr.h
+++ b/tb/sw/tl2cdr/tl2cdr.h
@@ -22,6 +22,7 @@
 #define CDR_WriteSoftReset 0x10
 #define CDR_ReadRxLen      0x18
 #define CDR_ReadRxFifo     0x1c
+#define CDR_ReadIsLast     0x20
 
 extern volatile uint32_t *cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
 extern volatile uint32_t *cdr_txLen  = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
@@ -30,6 +31,7 @@ extern volatile uint32_t *cdr_direct = (uint32_t*)( TL2CDR_BASE + CDR_WriteTrans
 extern volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
 extern volatile uint32_t *cdr_rxLen     = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
 extern volatile uint32_t *cdr_rxFifo    = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
+extern volatile uint32_t *cdr_IsLast    = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
 // extern uint8_t gpio_read();
 // extern uint32_t gpio_write( uint32_t data );