tl2cdr增加附带io

src/main/scala/backBoard/ebus/TL2CDR.scala

@@ -46,6 +46,9 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba
     val tld = new DecoupledIO(new TLBundleD(edge.bundle))
 
     val interrupt = Output(Vec(4, Bool()))
+
+    val isOnline = Output(Bool())
+    val isLast   = Input(Bool())
   }
 
   val io: TLCDRIO = IO(new TLCDRIO)
@@ -226,7 +229,17 @@ trait TL2CDRRx{ this: TL2CDRBase =>
 
 }
 
-class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) with TL2CDRTx with TL2CDRRx{
+trait TL2CDRIsLast{ this: TL2CDRBase =>
+  io.isOnline := false.B
+  val isReadIsLast = io.tla.fire & io.tla.bits.address(5,0) === "h20".U & io.tla.bits.opcode === 4.U
+
+}
+
+
+class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge)
+with TL2CDRTx with TL2CDRRx
+with TL2CDRIsLast
+{
 
   // val isWriteTransDir       = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
   val isWriteTransDir       = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
@@ -287,6 +300,8 @@ class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) wi
     rdata := rxLen
   } .elsewhen(isTLReadRxFifo      ){
     rdata := rxFifo.io.deq.bits
+  } .elsewhen(isReadIsLast){
+    rdata := io.isLast
   }