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spi格式修改

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This commit is contained in:
RuigeLee
2024-07-02 19:18:02 +08:00
parent e0bfd59539
commit bcbaa5b39b
2 changed files with 17 additions and 7 deletions
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21
src/main/scala/backBoard/SpiSlv.scala
View File

@@ -68,24 +68,26 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
bitSel := 0.U bitSel := 0.U
byteSel := 0.U byteSel := 0.U
cmd_100M := 0.U cmd_100M := 0.U
exReg_100M := 0.U exReg_100M := upReg(0)
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){
cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) ) cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
} .elsewhen( isSckNegedge & ~shiftCSn(1) & bitSel === 0.U ){ } .elsewhen( isSckNegedge & ~shiftCSn(1) & bitSel === 0.U ){
when( byteSel === 2.U & spiCmd === 2.U ){ when( byteSel === 1.U ){
exReg_100M := upReg(1)
} .elsewhen( spiCmd === 2.U & byteSel === 2.U ){
exReg_100M := localUpdate(7,0) exReg_100M := localUpdate(7,0)
} .elsewhen( byteSel === 3.U & spiCmd === 2.U ){ } .elsewhen( spiCmd === 2.U & byteSel === 3.U ){
exReg_100M := localUpdate(15,8) exReg_100M := localUpdate(15,8)
} .elsewhen( spiCmd === 0.U ){ } .elsewhen( spiCmd === 0.U & (byteSel =/= 0.U | byteSel =/= 1.U) ){
exReg_100M := spiRegDown.io.datar exReg_100M := spiRegDown.io.datar
} }
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel =/= 0.U ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel =/= 0.U ){
exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) ) exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
} }
when( isSckNegedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U & spiCmd === 3.U ){ when( isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
exMask_100M := Cat( exReg_100M, exMask_100M(7,0) ) exMask_100M := Cat( exReg_100M, exMask_100M(7,0) )
} .elsewhen( isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){ } .elsewhen( isSckNegedge & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){
exMask_100M := Cat( exMask_100M(15,8), exReg_100M ) exMask_100M := Cat( exMask_100M(15,8), exReg_100M )
} }
@@ -106,6 +108,7 @@ with BackBoardSpiSlv{
val csn = Input(Bool()) val csn = Input(Bool())
}) })
val clk100MIO = IO(Input(Bool())) val clk100MIO = IO(Input(Bool()))
val interrupt = IO(Output(Bool()))
sck := spi.sck sck := spi.sck
mosi := spi.mosi mosi := spi.mosi
@@ -136,6 +139,12 @@ with BackBoardSpiSlv{
io.lvdsSlv.upstream_tx_data_in := io.lvdsSlv.upstream_tx_data_in :=
Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar) Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
val int = RegInit(false.B); interrupt := int
when( int ){
int := false.B
} .elsewhen( RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & ~io.lvdsSlv.upstream_tx_data_ready ){
int := true.B
}
} }

3
src/main/verilog/spi_top.v
View File

@@ -309,7 +309,8 @@ SpiSlv i_spiSlv(
.spi_mosi(mosi), .spi_mosi(mosi),
.spi_miso(miso), .spi_miso(miso),
.spi_csn(csn), .spi_csn(csn),
.clk100MIO(clk_100m_a) .clk100MIO(clk_100m_a),
.interrupt()
); );