diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala
index 380fd49..7a19cb0 100644
--- a/src/main/scala/backBoard/SpiSlv.scala
+++ b/src/main/scala/backBoard/SpiSlv.scala
@@ -68,24 +68,26 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
       bitSel   := 0.U
       byteSel  := 0.U
       cmd_100M := 0.U
-      exReg_100M := 0.U
+      exReg_100M := upReg(0)
     } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){
       cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
     } .elsewhen( isSckNegedge & ~shiftCSn(1) & bitSel === 0.U ){
-      when( byteSel === 2.U & spiCmd === 2.U ){
+      when( byteSel === 1.U ){
+        exReg_100M := upReg(1)
+      } .elsewhen( spiCmd === 2.U & byteSel === 2.U ){
         exReg_100M := localUpdate(7,0)
-      } .elsewhen( byteSel === 3.U & spiCmd === 2.U ){
+      } .elsewhen( spiCmd === 2.U & byteSel === 3.U ){
         exReg_100M := localUpdate(15,8)
-      } .elsewhen( spiCmd === 0.U ){
+      } .elsewhen( spiCmd === 0.U & (byteSel =/= 0.U | byteSel =/= 1.U) ){
         exReg_100M := spiRegDown.io.datar
       }
     } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel =/= 0.U ){
       exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
     }
 
-    when(  isSckNegedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U & spiCmd === 3.U ){
+    when(  isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
       exMask_100M := Cat( exReg_100M, exMask_100M(7,0) )
-    } .elsewhen(  isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
+    } .elsewhen(  isSckNegedge & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){
       exMask_100M := Cat( exMask_100M(15,8), exReg_100M )
     }
 
@@ -106,6 +108,7 @@ with BackBoardSpiSlv{
     val csn  = Input(Bool())
   })
   val clk100MIO = IO(Input(Bool()))
+  val interrupt = IO(Output(Bool()))
 
   sck  := spi.sck
   mosi := spi.mosi
@@ -136,6 +139,12 @@ with BackBoardSpiSlv{
   io.lvdsSlv.upstream_tx_data_in :=
     Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
 
+  val int = RegInit(false.B); interrupt := int
+  when( int ){
+    int := false.B
+  } .elsewhen( RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & ~io.lvdsSlv.upstream_tx_data_ready ){
+    int := true.B
+  }
 
 
 }
diff --git a/src/main/verilog/spi_top.v b/src/main/verilog/spi_top.v
index bf15e40..3a2b6ef 100644
--- a/src/main/verilog/spi_top.v
+++ b/src/main/verilog/spi_top.v
@@ -309,7 +309,8 @@ SpiSlv i_spiSlv(
   .spi_mosi(mosi),
   .spi_miso(miso),
   .spi_csn(csn),
-  .clk100MIO(clk_100m_a)
+  .clk100MIO(clk_100m_a),
+  .interrupt()
 );