spi格式修改
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@@ -68,24 +68,26 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
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bitSel := 0.U
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byteSel := 0.U
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cmd_100M := 0.U
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exReg_100M := 0.U
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exReg_100M := upReg(0)
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} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){
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cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
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} .elsewhen( isSckNegedge & ~shiftCSn(1) & bitSel === 0.U ){
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when( byteSel === 2.U & spiCmd === 2.U ){
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when( byteSel === 1.U ){
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exReg_100M := upReg(1)
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} .elsewhen( spiCmd === 2.U & byteSel === 2.U ){
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exReg_100M := localUpdate(7,0)
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} .elsewhen( byteSel === 3.U & spiCmd === 2.U ){
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} .elsewhen( spiCmd === 2.U & byteSel === 3.U ){
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exReg_100M := localUpdate(15,8)
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} .elsewhen( spiCmd === 0.U ){
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} .elsewhen( spiCmd === 0.U & (byteSel =/= 0.U | byteSel =/= 1.U) ){
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exReg_100M := spiRegDown.io.datar
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}
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} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel =/= 0.U ){
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exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
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}
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when( isSckNegedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U & spiCmd === 3.U ){
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when( isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
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exMask_100M := Cat( exReg_100M, exMask_100M(7,0) )
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} .elsewhen( isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
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} .elsewhen( isSckNegedge & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){
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exMask_100M := Cat( exMask_100M(15,8), exReg_100M )
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}
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@@ -106,6 +108,7 @@ with BackBoardSpiSlv{
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val csn = Input(Bool())
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})
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val clk100MIO = IO(Input(Bool()))
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val interrupt = IO(Output(Bool()))
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sck := spi.sck
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mosi := spi.mosi
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@@ -136,6 +139,12 @@ with BackBoardSpiSlv{
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io.lvdsSlv.upstream_tx_data_in :=
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Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
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val int = RegInit(false.B); interrupt := int
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when( int ){
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int := false.B
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} .elsewhen( RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & ~io.lvdsSlv.upstream_tx_data_ready ){
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int := true.B
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}
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}
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