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修改pllctrl复位默认值

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This commit is contained in:
Ruige Lee
2025-08-25 14:30:15 +08:00
parent 976c468b6a
commit bca9724c3c
1 changed files with 6 additions and 6 deletions
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12
src/main/scala/backBoard/shin/Interface.scala
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@@ -1299,16 +1299,16 @@ trait InterfaceEvent{ this: InterfaceBase =>
trait InterfaceAnalog{ this: InterfaceBase => trait InterfaceAnalog{ this: InterfaceBase =>
cReg.pllCtrl := cReg.pllCtrl :=
Cat( Cat(
RegEnable( dataw, "b10000000".U(8.W), isEnW & addrw === "h47".U ), RegEnable( dataw, "h80".U(8.W), isEnW & addrw === "h47".U ),
RegEnable( dataw, "b00000000".U(8.W), isEnW & addrw === "h46".U ), RegEnable( dataw, "h00".U(8.W), isEnW & addrw === "h46".U ),
RegEnable( dataw, "b00110001".U(8.W), isEnW & addrw === "h45".U ), RegEnable( dataw, "h31".U(8.W), isEnW & addrw === "h45".U ),
RegEnable( dataw, "b01011101".U(8.W), isEnW & addrw === "h44".U ) RegEnable( dataw, "h3c".U(8.W), isEnW & addrw === "h44".U )
) )
cReg.xtal := cReg.xtal :=
Cat( Cat(
RegEnable( dataw, "b00000101".U(8.W), isEnW & addrw === "h49".U ), RegEnable( dataw, "h05".U(8.W), isEnW & addrw === "h49".U ),
RegEnable( dataw, "b00010101".U(8.W), isEnW & addrw === "h48".U ) RegEnable( dataw, "h15".U(8.W), isEnW & addrw === "h48".U )
) )