From bca9724c3c20b8dc5c8bb34e0378a7fac8993782 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 25 Aug 2025 14:30:15 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9pllctrl=E5=A4=8D=E4=BD=8D?= =?UTF-8?q?=E9=BB=98=E8=AE=A4=E5=80=BC?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 9618bee..d64aca5 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -1299,16 +1299,16 @@ trait InterfaceEvent{ this: InterfaceBase => trait InterfaceAnalog{ this: InterfaceBase => cReg.pllCtrl := Cat( - RegEnable( dataw, "b10000000".U(8.W), isEnW & addrw === "h47".U ), - RegEnable( dataw, "b00000000".U(8.W), isEnW & addrw === "h46".U ), - RegEnable( dataw, "b00110001".U(8.W), isEnW & addrw === "h45".U ), - RegEnable( dataw, "b01011101".U(8.W), isEnW & addrw === "h44".U ) + RegEnable( dataw, "h80".U(8.W), isEnW & addrw === "h47".U ), + RegEnable( dataw, "h00".U(8.W), isEnW & addrw === "h46".U ), + RegEnable( dataw, "h31".U(8.W), isEnW & addrw === "h45".U ), + RegEnable( dataw, "h3c".U(8.W), isEnW & addrw === "h44".U ) ) cReg.xtal := Cat( - RegEnable( dataw, "b00000101".U(8.W), isEnW & addrw === "h49".U ), - RegEnable( dataw, "b00010101".U(8.W), isEnW & addrw === "h48".U ) + RegEnable( dataw, "h05".U(8.W), isEnW & addrw === "h49".U ), + RegEnable( dataw, "h15".U(8.W), isEnW & addrw === "h48".U ) )