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加入测试led方便FPGA测试，最终版请撤销本提交

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This commit is contained in:
Ruige Lee
2025-05-22 19:45:07 +08:00
parent df0eeeb956
commit bc7cf31916
2 changed files with 9 additions and 3 deletions
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6
src/main/scala/backBoard/shin/Interface.scala
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@@ -434,16 +434,16 @@ trait InterfaceMCUop{ this: InterfaceBase =>
cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U ) cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U )
cReg.hwVersion := RegEnable( dataw , 0.U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U ) cReg.hwVersion := RegEnable( dataw , "hF0".U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U )
cReg.hwSerial := cReg.hwSerial :=
Cat( Cat(
(0 until 6).map{ i => (0 until 6).map{ i =>
RegEnable( dataw, 0.U, isEnW & addrw === ("h2".U + i.U) & cReg.mstOrSlv === 0.U ) RegEnable( dataw, "haa".U, isEnW & addrw === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
}.reverse }.reverse
) )
cReg.busRate := RegEnable( dataw, 0.U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U ) cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U ) cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
cReg.encryptKey := cReg.encryptKey :=

6
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -45,6 +45,7 @@ class ShinTopIO extends Bundle{
val oSync = Output(Vec(4, Bool())) val oSync = Output(Vec(4, Bool()))
val isSoftReset = Output(Bool()) val isSoftReset = Output(Bool())
val ledTest = Output(UInt(8.W))
} }
@@ -58,6 +59,8 @@ abstract class ShinTopBase extends Module{
// val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } // val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
val slaveParser = Module(new SlaveParser ) val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser) val masterParser = Module(new MasterParser)
@@ -67,6 +70,9 @@ abstract class ShinTopBase extends Module{
val upCDROut = Module(new CDROut) val upCDROut = Module(new CDROut)
val interface = Module(new Interface) val interface = Module(new Interface)
io.ledTest := RegNext( interface.io.cReg.hwVersion(7,0), "h55".U )
io.isSoftReset := interface.io.isSoftReset io.isSoftReset := interface.io.isSoftReset
downCDRIn.io.serDat := io.dDatIn downCDRIn.io.serDat := io.dDatIn