From bc7cf319168a4edcf0cc8efc591332c2af228c21 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Thu, 22 May 2025 19:45:07 +0800
Subject: [PATCH] =?UTF-8?q?=E5=8A=A0=E5=85=A5=E6=B5=8B=E8=AF=95led?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 6 +++---
 src/main/scala/backBoard/shin/ShinTop.scala   | 6 ++++++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 7a96341..b7bacb5 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -434,16 +434,16 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
 
   cReg.mstOrSlv  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U )
-  cReg.hwVersion := RegEnable( dataw     , 0.U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U )
+  cReg.hwVersion := RegEnable( dataw     , "hF0".U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U )
 
   cReg.hwSerial := 
     Cat(
       (0 until 6).map{ i =>
-      RegEnable( dataw, 0.U, isEnW & addrw === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
+      RegEnable( dataw, "haa".U, isEnW & addrw === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
       }.reverse
     )
   
-  cReg.busRate := RegEnable( dataw, 0.U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
+  cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
   cReg.spiSel  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
 
   cReg.encryptKey :=
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 4b63d66..e35412d 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -45,6 +45,7 @@ class ShinTopIO extends Bundle{
   val oSync = Output(Vec(4, Bool()))
 
   val isSoftReset = Output(Bool())
+  val ledTest = Output(UInt(8.W))
 }
 
 
@@ -58,6 +59,8 @@ abstract class ShinTopBase extends Module{
   // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
 	// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
 
+
+
 	val slaveParser  = Module(new SlaveParser )
 	val masterParser = Module(new MasterParser)
 
@@ -67,6 +70,9 @@ abstract class ShinTopBase extends Module{
   val upCDROut   = Module(new CDROut)
 
   val interface = Module(new Interface)
+
+  io.ledTest := RegNext( interface.io.cReg.hwVersion(7,0), "h55".U )
+  
   io.isSoftReset := interface.io.isSoftReset
 
   downCDRIn.io.serDat  := io.dDatIn