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加入测试led方便FPGA测试，最终版请撤销本提交

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This commit is contained in:
Ruige Lee
2025-05-22 19:45:07 +08:00
parent df0eeeb956
commit bc7cf31916
2 changed files with 9 additions and 3 deletions
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6
src/main/scala/backBoard/shin/Interface.scala
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@@ -434,16 +434,16 @@ trait InterfaceMCUop{ this: InterfaceBase =>
cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U )
cReg.hwVersion := RegEnable( dataw , 0.U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U )
cReg.hwVersion := RegEnable( dataw , "hF0".U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U )
cReg.hwSerial :=
Cat(
(0 until 6).map{ i =>
RegEnable( dataw, 0.U, isEnW & addrw === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
RegEnable( dataw, "haa".U, isEnW & addrw === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
}.reverse
)
cReg.busRate := RegEnable( dataw, 0.U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
cReg.encryptKey :=