增加CDR仿真例程

2025-08-28 20:03:42 +08:00
parent 55ea876488
commit bbfc0322e9
3 changed files with 94 additions and 0 deletions
--- a/12
+++ b/12
@@ -53,6 +53,18 @@ testShin:
 	vvp  -N ./tb/build/shinTest.iverilog -lxt2 || true
 	./tb/shinTest/check_testcase.py

+testCDR:
+	iverilog -Wall  \
+	-o ./tb/build/simCDR.iverilog  \
+	-y ./generated/shin \
+	-y ./generated/SimCDR \
+	-I ./generated/SimCDR \
+	-I ./generated/shin \
+	-D RANDOMIZE_REG_INIT \
+	./tb/shinTest/SimCDRTb.v 
+	vvp  -N ./tb/build/simCDR.iverilog -lxt2
+
+
 testFilter:
 	./tb/shinTest/test_filter.py