diff --git a/Makefile b/Makefile
index 8b0779e..ffd15f6 100644
--- a/Makefile
+++ b/Makefile
@@ -53,6 +53,18 @@ testShin:
 	vvp  -N ./tb/build/shinTest.iverilog -lxt2 || true
 	./tb/shinTest/check_testcase.py
 
+testCDR:
+	iverilog -Wall  \
+	-o ./tb/build/simCDR.iverilog  \
+	-y ./generated/shin \
+	-y ./generated/SimCDR \
+	-I ./generated/SimCDR \
+	-I ./generated/shin \
+	-D RANDOMIZE_REG_INIT \
+	./tb/shinTest/SimCDRTb.v 
+	vvp  -N ./tb/build/simCDR.iverilog -lxt2
+
+
 testFilter:
 	./tb/shinTest/test_filter.py
 
diff --git a/src/test/scala/SimCDR.scala b/src/test/scala/SimCDR.scala
new file mode 100644
index 0000000..a9d10ef
--- /dev/null
+++ b/src/test/scala/SimCDR.scala
@@ -0,0 +1,77 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+class SimCDR extends Module with RequireAsyncReset{
+  val io = IO(new Bundle{
+    val data = Input( UInt(8.W) )
+
+    val multiCLK = Input(Vec(16, Bool()))
+
+    val flush = Input(Bool())
+
+    val isSuccess = Output(Bool())
+    val isFailed = Output(Bool())
+  })
+
+
+
+
+  val cdrIn = Module(new MPCDRIn)
+  val cdrOut = Module(new CDROut)
+  val record = Module( new Queue(UInt(8.W), 256) )
+
+  val dataCnt = RegInit(0.U(12.W))
+  val payloadLen = RegInit(("hFFF".U)(12.W))
+
+   
+  when( cdrOut.io.axis.fire & dataCnt === 0.U ){
+    payloadLen := Cat( io.data, 0.U(4.W) )
+  } .elsewhen( cdrOut.io.axis.fire & dataCnt === 1.U ){
+    payloadLen := Cat( payloadLen(11,4), io.data(7,4) ) + 4.U + 4.U
+  }
+
+  when( cdrOut.io.axis.fire ){
+    when( dataCnt >= payloadLen - 1.U ){
+      dataCnt := 0.U
+    } .otherwise{
+      dataCnt := dataCnt + 1.U
+    }
+  }
+
+
+  cdrOut.io.flush := io.flush
+
+  cdrIn.clock := io.multiCLK(0).asClock
+  cdrIn.io.flush := io.flush
+  cdrIn.multiCLK := io.multiCLK
+
+  cdrIn.io.serDat := cdrOut.io.serDat
+
+  assert( ~(record.io.enq.valid  & ~record.io.enq.ready), "Assert Failed, Warning, fifo overflow!\n" )
+  assert( ~(~record.io.deq.valid & record.io.deq.ready),  "Assert Failed, Warning, fifo underflow!\n" )
+
+  val isTxEnd = cdrOut.io.axis.fire & cdrOut.io.axis.bits.tlast
+
+  cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 16 ).reduce(_&_)
+  cdrOut.io.axis.bits.tdata  := io.data
+  cdrOut.io.axis.bits.tuser  := false.B
+  cdrOut.io.axis.bits.tlast  := dataCnt === (payloadLen - 1.U)
+
+
+
+  record.io.enq.valid := cdrOut.io.axis.fire
+  record.io.enq.bits  := io.data
+
+  record.io.deq.ready := cdrIn.io.axis.fire
+  cdrIn.io.axis.ready := true.B
+
+  io.isFailed  := cdrIn.io.axis.fire & (record.io.deq.bits =/= cdrIn.io.axis.bits.tdata)
+  io.isSuccess := cdrIn.io.axis.fire & cdrIn.io.axis.bits.tlast
+
+}
+
+
diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala
index e04999d..3705673 100644
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -103,6 +103,11 @@ object testShinModule extends App {
       ChiselGeneratorAnnotation(() => { new ShinTop }),
     ))
 
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/SimCDR/", "-e", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new SimCDR }),
+    ))
+    
+
 
 }