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CDR发送测试完成

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RuigeLee
2024-09-11 17:21:14 +08:00
parent 7350f3bcf4
commit ba6099608c
2 changed files with 3 additions and 463 deletions
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6
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -49,9 +49,9 @@ class CDROut extends Module{
stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( byteCnt === 7.U & bitCnt === 7.U, STATE_PAYLOAD, STATE_PREAMBLE )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_FCS ) ),
(stateCurr === STATE_FCS) -> ( Mux( byteCnt === 3.U & bitCnt === 7.U, STATE_FCS, STATE_IDLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_PREAMBLE )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ),
(stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 7.U), STATE_IDLE, STATE_FCS )),
))
io.serDat := shiftData.extract(7)