Revert "从机上下行机制分叉"

This reverts commit a9f4fd18ab.

src/main/scala/backBoard/BackBoardSlv.scala

@@ -32,8 +32,6 @@ abstract class BackBoardSlvBase extends Module{
   
   val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
   val upReg       = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
-
-  val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err
 }
 
 
@@ -50,7 +48,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
     downCnt := 0.U
   }
 
-
+  val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err
 
   // when( io.lvdsSlv.downstream_rx_crc_valid ){
   //   when( ~io.lvdsSlv.downstream_rx_crc_err ){