From b696723e23b514c2ee70e295e51ee8cf896d301d Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 28 Jun 2024 15:22:44 +0800 Subject: [PATCH] =?UTF-8?q?Revert=20"=E4=BB=8E=E6=9C=BA=E4=B8=8A=E4=B8=8B?= =?UTF-8?q?=E8=A1=8C=E6=9C=BA=E5=88=B6=E5=88=86=E5=8F=89"?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit a9f4fd18abd3c8b591fa69008867f68791f6975a. --- src/main/scala/backBoard/BackBoardSlv.scala | 4 +--- src/main/scala/backBoard/DIn16.scala | 2 +- src/main/scala/backBoard/Dout16.scala | 2 +- src/main/scala/backBoard/LocalRegisters.scala | 2 +- src/main/scala/backBoard/Qei.scala | 3 +-- 5 files changed, 5 insertions(+), 8 deletions(-) diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala index cd30a16..6ae0c7e 100644 --- a/src/main/scala/backBoard/BackBoardSlv.scala +++ b/src/main/scala/backBoard/BackBoardSlv.scala @@ -32,8 +32,6 @@ abstract class BackBoardSlvBase extends Module{ val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} )) val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)})) - - val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err } @@ -50,7 +48,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase => downCnt := 0.U } - + val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err // when( io.lvdsSlv.downstream_rx_crc_valid ){ // when( ~io.lvdsSlv.downstream_rx_crc_err ){ diff --git a/src/main/scala/backBoard/DIn16.scala b/src/main/scala/backBoard/DIn16.scala index 22c3e23..4f0a135 100644 --- a/src/main/scala/backBoard/DIn16.scala +++ b/src/main/scala/backBoard/DIn16.scala @@ -112,7 +112,7 @@ trait BackBoardSlvIn16 { this: BackBoardSlvLocal => -class DIn16 extends BackBoardSlvLocal with BackBoardSlvDown with BackBoardSlvUp +class DIn16 extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvIn16{ diff --git a/src/main/scala/backBoard/Dout16.scala b/src/main/scala/backBoard/Dout16.scala index b56988a..351e75e 100644 --- a/src/main/scala/backBoard/Dout16.scala +++ b/src/main/scala/backBoard/Dout16.scala @@ -19,7 +19,7 @@ trait BackBoardSlvOut16{ this: BackBoardSlvLocal => } -class DOut16 extends BackBoardSlvLocal with BackBoardSlvDown with BackBoardSlvUp +class DOut16 extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvOut16{ val out = IO(Output(UInt(16.W))) diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index 1db5cf2..3e2b8d7 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -12,7 +12,7 @@ class ManualParamBundle extends Bundle{ } -abstract class BackBoardSlvLocal extends BackBoardSlvBase{ +abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{ val param = IO(Input( new ManualParamBundle )) diff --git a/src/main/scala/backBoard/Qei.scala b/src/main/scala/backBoard/Qei.scala index 248f030..4b6c611 100644 --- a/src/main/scala/backBoard/Qei.scala +++ b/src/main/scala/backBoard/Qei.scala @@ -96,8 +96,7 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal => } -class Qei extends BackBoardSlvLocal with BackBoardSlvDown with BackBoardSlvUp -with BackBoardSlvStatusPR with BackBoardSlvQei{ +class Qei extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvQei{ val phaseAIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) } val phaseBIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) } val phaseZIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }