dma通路完成，可以承载背靠背负载

src/main/scala/Switch/mac/MacTileLinkTx.scala

@@ -38,6 +38,8 @@ class MacTileLinkTxIO extends Bundle{
   
   val txDeq = Flipped(Decoupled(new Mac_Stream_Bundle))
 
+  val isTxIdle = Input(Bool())
+
 }
 
 
@@ -71,7 +73,7 @@ class MacTileLinkTx extends Module{
       Flop := ~Flop
     }
     
-    when( asyncReqBundle.valid & asyncReqBundle.bits.isStart ){
+    when( asyncReqBundle.valid & asyncReqBundle.bits.isStart & ~TxStartFrm & io.isTxIdle ){
       TxStartFrm := true.B
     } .elsewhen(TxUsedData_q | io.TxAbort & (~TxAbort_q) ){
       TxStartFrm := false.B
@@ -89,7 +91,7 @@ class MacTileLinkTx extends Module{
 
 
     asyncReqBundle.ready := 
-        asyncReqBundle.valid & asyncReqBundle.bits.isStart & ~TxStartFrm |
+        asyncReqBundle.valid & asyncReqBundle.bits.isStart & ~TxStartFrm & io.isTxIdle |
         io.TxUsedData & Flop & ~TxEndFrm |
         TxStartFrm & io.TxUsedData & Flop
 

src/main/scala/Switch/mac/MacTx.scala

@@ -33,7 +33,9 @@ class MacTxIO extends Bundle{
   val LateCollision      = Output(Bool())
   val DeferIndication    = Output(Bool())
   val StatePreamble      = Output(Bool())
-  val StateData          = Output(UInt(2.W))    
+  val StateData          = Output(UInt(2.W))
+
+  val isTxIdle = Output(Bool())
 }
 
 abstract class MacTxBase extends Module with RequireAsyncReset{
@@ -78,6 +80,7 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
   val NibCntEq7  = NibCnt === 7.U
   val NibCntEq15 = NibCnt === 15.U
 
+  io.isTxIdle := StateIdle
 }