diff --git a/src/main/scala/Switch/DMA.scala b/src/main/scala/Switch/DMA.scala
index 0ebdfd9..de6ca8c 100644
--- a/src/main/scala/Switch/DMA.scala
+++ b/src/main/scala/Switch/DMA.scala
@@ -54,7 +54,7 @@ trait DMAMstFSM{ this: DMAMstBase =>
 
   stateNxt := 
     Mux1H(Seq(
-      ( stateCur === stateIdle ) -> Mux( (0 until chn).map{i => (io.cfg(i).triTx & io.cfg(i).r_TxLen > 32.U)}.foldLeft(false.B)(_|_) , stateTx, Mux( rxBuff.mInfo.source.valid, stateRx, stateIdle ) ),
+      ( stateCur === stateIdle ) -> Mux( (0 until chn).map{i => (io.cfg(i).triTx & io.cfg(i).r_TxLen > 32.U)}.foldLeft(false.B)(_|_) , stateTx, Mux( txBuff.io.deq.valid, stateRx, stateIdle ) ),
       ( stateCur === stateRx   ) -> Mux( stateDMA === 0.U, stateIdle, stateRx ),
       ( stateCur === stateTx   ) -> Mux( stateDMA === 0.U, stateIdle, stateTx ),
     ))
@@ -67,7 +67,7 @@ trait DMAMstFSM{ this: DMAMstBase =>
   } .elsewhen( io.dmaMst.D.fire & isLastD ){
     when( stateCur === stateTx & dmaAddress === (io.cfg(trigTxNum).r_TxPtr + io.cfg(trigTxNum).r_TxLen) ){
       stateDMA := 0.U
-    } .elsewhen( stateCur === stateRx & ~rxBuff.io.deq.valid  ){
+    } .elsewhen( stateCur === stateRx & ~txBuff.io.deq.valid  ){
       stateDMA := 0.U
     } .otherwise{
       stateDMA := 1.U
@@ -83,7 +83,7 @@ trait DMAMstTileLink{ this: DMAMstBase =>
 
   val mInfoValid = stateCur === stateTx
 
-  when( rxBuff.mInfo.source.valid & stateCur === stateIdle & stateNxt === stateRx  ){
+  when( txBuff.io.deq.valid & stateCur === stateIdle & stateNxt === stateRx  ){
 
     trigRxNum := io.selIn
 
@@ -91,7 +91,7 @@ trait DMAMstTileLink{ this: DMAMstBase =>
   }
 
   for( i <- 0 until chn ){
-    io.cfg(i).triRx   := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast & trigRxNum === i.U
+    io.cfg(i).triRx   := txBuff.io.deq.fire & txBuff.io.deq.bits.isLast & trigRxNum === i.U
     io.cfg(i).r_RxLen := RegEnable( rxLength + 1.U, io.cfg(i).triRx )
   }
 
@@ -107,8 +107,8 @@ trait DMAMstTileLink{ this: DMAMstBase =>
     dmaAddress := dmaAddress + 1.U
   }
 
-  rxBuff.io.deq.ready := io.dmaMst.A.fire & (stateCur === stateRx)
-  assert( ~(rxBuff.io.deq.ready & ~rxBuff.io.deq.valid) )
+  txBuff.io.deq.ready := io.dmaMst.A.fire & (stateCur === stateRx)
+  assert( ~(txBuff.io.deq.ready & ~txBuff.io.deq.valid) )
 
   when( io.dmaMst.A.fire ){
     dmaAValid := false.B
@@ -127,7 +127,7 @@ trait DMAMstTileLink{ this: DMAMstBase =>
         fromSource = 0.U,
         toAddress = dmaAddress,
         lgSize = log2Ceil(8/8).U,
-        data = rxBuff.io.deq.bits.data,
+        data = txBuff.io.deq.bits.data,
         mask = "b1".U,
       )._2
   }
@@ -140,7 +140,7 @@ trait DMAMstTileLink{ this: DMAMstBase =>
   io.dmaMst.D.ready := 
     Mux1H(Seq(
       ( stateCur === stateRx ) -> true.B,
-      ( stateCur === stateTx ) -> txBuff.io.enq.ready,
+      ( stateCur === stateTx ) -> rxBuff.io.enq.ready,
     ))
 }
 
@@ -148,8 +148,8 @@ trait DMAMstBuff{ this: DMAMstBase =>
 
 
 
-  when( rxBuff.io.deq.fire ){
-    when( rxBuff.io.deq.bits.isStart ){
+  when( txBuff.io.deq.fire ){
+    when( txBuff.io.deq.bits.isStart ){
       rxLength := 0.U
     } .otherwise{
       rxLength := rxLength + 1.U
@@ -159,10 +159,10 @@ trait DMAMstBuff{ this: DMAMstBase =>
 
 
 
-  txBuff.io.enq.valid := io.dmaMst.D.valid & stateCur === stateTx
-  txBuff.io.enq.bits.data  := io.dmaMst.D.bits.data
-  txBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.cfg(trigTxNum).r_TxPtr, io.dmaMst.A.fire)
-  txBuff.io.enq.bits.isLast  := dmaAddress === (io.cfg(trigTxNum).r_TxPtr + io.cfg(trigTxNum).r_TxLen)
+  rxBuff.io.enq.valid := io.dmaMst.D.valid & stateCur === stateTx
+  rxBuff.io.enq.bits.data  := io.dmaMst.D.bits.data
+  rxBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.cfg(trigTxNum).r_TxPtr, io.dmaMst.A.fire)
+  rxBuff.io.enq.bits.isLast  := dmaAddress === (io.cfg(trigTxNum).r_TxPtr + io.cfg(trigTxNum).r_TxLen)
 
   io.selOut := trigTxNum
 
diff --git a/src/main/scala/Switch/MAC.scala b/src/main/scala/Switch/MAC.scala
index 5fc4171..cc1b5c6 100644
--- a/src/main/scala/Switch/MAC.scala
+++ b/src/main/scala/Switch/MAC.scala
@@ -419,7 +419,7 @@ abstract class Mac(implicit p: Parameters) extends SwitchNode{
 
   macTileLinkTx.io.r_TxEn    := r_TxEn
 
-
+  macTileLinkTx.io.isTxIdle := txethmac.io.isTxIdle
 
   macTileLinkTx.io.MTxClk     := io.mii.mtx_clk_pad_i
   macTileLinkTx.io.asyncReset := io.asyncReset
diff --git a/src/main/scala/Switch/Robin.scala b/src/main/scala/Switch/Robin.scala
index fef75d4..3c7723b 100644
--- a/src/main/scala/Switch/Robin.scala
+++ b/src/main/scala/Switch/Robin.scala
@@ -34,7 +34,7 @@ class Robin(implicit p: Parameters) extends SwitchModule{
   val lockChn = Reg(UInt((log2Ceil(chn+1)).W))
   io.sel := lockChn
 
-  val lfsr = ~LFSR( log2Ceil(chn+1), ~isLock)
+  val lfsr = ~LFSR( (log2Ceil(chn+1)+1), ~isLock)
 
   for( i <- 0 until chn+1 ) {
     when( i.U === lfsr ){
diff --git a/src/main/scala/Switch/SwitchNode.scala b/src/main/scala/Switch/SwitchNode.scala
index 54e05ad..4f66de4 100644
--- a/src/main/scala/Switch/SwitchNode.scala
+++ b/src/main/scala/Switch/SwitchNode.scala
@@ -50,13 +50,13 @@ class MacNode(implicit p: Parameters) extends Mac{
 class DmaNode(edgeOut: TLEdgeOut)(implicit p: Parameters) extends DMAMst(edgeOut){
   // def DmaMac = "habcdef".U(48.W)
 
-  ex.tx <> rxBuff.io.enq
-  txBuff.io.deq <> ex.rx
+  ex.tx <> txBuff.io.enq
+  rxBuff.io.deq <> ex.rx
 
-  ex.mInfo.dest.valid := mInfoValid
-  ex.mInfo.dest.bits  := DontCare
-  ex.mInfo.source.valid := mInfoValid
-  ex.mInfo.source.bits  := DontCare
+  ex.mInfo.dest.valid := rxBuff.mInfo.dest.valid
+  ex.mInfo.dest.bits  := 0.U
+  ex.mInfo.source.valid := rxBuff.mInfo.source.valid
+  ex.mInfo.source.bits  := 0.U
 
 }
 
diff --git a/src/main/scala/Switch/WithSwitch.scala b/src/main/scala/Switch/WithSwitch.scala
index bf30930..ef79442 100644
--- a/src/main/scala/Switch/WithSwitch.scala
+++ b/src/main/scala/Switch/WithSwitch.scala
@@ -16,11 +16,11 @@ trait WithSwitchMix { this: BaseSubsystem =>
     // pbus.coupleTo("switch_cfg")   { switch0.tlMasterNode := TLFragmenter(pbus) := _ }
 
     for( i <- 0 until 3 ){
-      pbus.coupleTo("switch_cfg")   { switch.macReg(i).configNode   := TLFragmenter(pbus) := _ }
+      pbus.coupleTo(s"mac_cfg$i")   { switch.macReg(i).configNode   := TLFragmenter(pbus) := _ }
       ibus.fromSync := switch.macReg(i).int_node   
     }
 
-    pbus.coupleTo("switch_cfg")   { switch.dmaReg.configNode   := TLFragmenter(pbus) := _ }
+    pbus.coupleTo("dma_cfg")   { switch.dmaReg.configNode   := TLFragmenter(pbus) := _ }
 
 
 
diff --git a/src/main/scala/Switch/mac/MacTileLinkTx.scala b/src/main/scala/Switch/mac/MacTileLinkTx.scala
index ece0a85..fda20fd 100644
--- a/src/main/scala/Switch/mac/MacTileLinkTx.scala
+++ b/src/main/scala/Switch/mac/MacTileLinkTx.scala
@@ -38,6 +38,8 @@ class MacTileLinkTxIO extends Bundle{
   
   val txDeq = Flipped(Decoupled(new Mac_Stream_Bundle))
 
+  val isTxIdle = Input(Bool())
+
 }
 
 
@@ -71,7 +73,7 @@ class MacTileLinkTx extends Module{
       Flop := ~Flop
     }
     
-    when( asyncReqBundle.valid & asyncReqBundle.bits.isStart ){
+    when( asyncReqBundle.valid & asyncReqBundle.bits.isStart & ~TxStartFrm & io.isTxIdle ){
       TxStartFrm := true.B
     } .elsewhen(TxUsedData_q | io.TxAbort & (~TxAbort_q) ){
       TxStartFrm := false.B
@@ -89,7 +91,7 @@ class MacTileLinkTx extends Module{
 
 
     asyncReqBundle.ready := 
-        asyncReqBundle.valid & asyncReqBundle.bits.isStart & ~TxStartFrm |
+        asyncReqBundle.valid & asyncReqBundle.bits.isStart & ~TxStartFrm & io.isTxIdle |
         io.TxUsedData & Flop & ~TxEndFrm |
         TxStartFrm & io.TxUsedData & Flop
 
diff --git a/src/main/scala/Switch/mac/MacTx.scala b/src/main/scala/Switch/mac/MacTx.scala
index 5ded4e8..c37f12c 100644
--- a/src/main/scala/Switch/mac/MacTx.scala
+++ b/src/main/scala/Switch/mac/MacTx.scala
@@ -33,7 +33,9 @@ class MacTxIO extends Bundle{
   val LateCollision      = Output(Bool())
   val DeferIndication    = Output(Bool())
   val StatePreamble      = Output(Bool())
-  val StateData          = Output(UInt(2.W))    
+  val StateData          = Output(UInt(2.W))
+
+  val isTxIdle = Output(Bool())
 }
 
 abstract class MacTxBase extends Module with RequireAsyncReset{
@@ -78,6 +80,7 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
   val NibCntEq7  = NibCnt === 7.U
   val NibCntEq15 = NibCnt === 15.U
 
+  io.isTxIdle := StateIdle
 }