临时解决方案

Makefile

@@ -12,13 +12,13 @@ compile:
 # 	sbt "test:runMain test.testModule"
 
 back:
-	rm -f ./generated/*
+	rm -f ./generated/back/*
 	sbt "test:runMain test.testModule"
-	cp ./src/main/verilog/backBoardMstTop.v ./generated/
+	cp ./src/main/verilog/backBoardMstTop.v ./generated/back/
-	cp ./src/main/verilog/oser_rst.v ./generated/
+	cp ./src/main/verilog/oser_rst.v ./generated/back/
-	cp ./src/main/verilog/di16_top.v ./generated/
+	cp ./src/main/verilog/di16_top.v ./generated/back/
-	cp ./src/main/verilog/do16_top.v ./generated/
+	cp ./src/main/verilog/do16_top.v ./generated/back/
-	cp ./src/main/verilog/defineParam.v ./generated/
+	cp ./src/main/verilog/defineParam.v ./generated/back/
 
 
 

src/main/verilog/backBoardMstTop.v

@@ -47,12 +47,23 @@ wire       reset_calib;
 wire lock_o;
 wire       reset_stop;
 
+wire       resetn1;
+
 always@(posedge clock) begin
   rstn_d <= resetn;
 	rst_n <= rstn_d;
 end
 
 
+reg [3:0] resetCnt = 4'd0;
+always @( posedge clock ) begin
+  if( resetCnt != 4'd15 ) begin
+    resetCnt <= resetCnt + 4'd1;
+  end
+end
+
+assign resetn1 = (resetCnt == 4'd15);
+
 Gowin_PLLO Gowin_PLLO(
     .lock(lock_o),
     .clkouta(clk_400m),
@@ -84,7 +95,7 @@ DHCEN dhcen_inst (
 //reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
 oser_rst u_oser_rst(
   .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
-  .rst_n(rst_n),
+  .rst_n(rst_n && resetn1),
   .pll_lock(lock_o), // trigged by PLL Lock
   .reset_stop(reset_stop), // for DHCEN CE
   .reset_calib(reset_calib), // for IDES and CLKDIV reset
@@ -141,7 +152,7 @@ wire [7:0] rx_data_out;
 wire rx_data_valid;
 
 lvds_bus_master_top i_lvds_bus_master(
-  .rst_n(rst_n),
+  .rst_n(rst_n && resetn1),
   .reset_calib(reset_calib),
   .oser_pclk(clk_10m_a),
   .oser_fclk(clk_50m_a),
@@ -193,7 +204,7 @@ BackBoardMst i_BackBoardMst(
   .io_FSMC_wrn(io_FSMC_wrn),
   .io_FSMC_advn(io_FSMC_advn),
 
-  .reset(~rst_n),
+  .reset(~resetn1),
   .clock(clk_10m_a),
   .io_oser_pclk(clk_10m_a),
   .io_oser_fclk(clk_50m_a),

src/main/verilog/di16_top.v

@@ -36,6 +36,16 @@ reg rst_n;
 reg rstn_d;
 
 wire resetn;
+reg  resetn1=1'b1;
+wire timeout_rst;
+reg timeout_rst_d1;
+reg timeout_rst_d2;
+reg timeout_rst_d3;
+reg timeout_rst_d4;
+reg timeout_rst_d5;
+reg timeout_rst_d6;
+reg timeout_rst_d7;
+reg timeout_rst_d8;
 
 reg [3:0] resetCnt = 4'd0;
 always @( posedge clock ) begin
@@ -46,11 +56,84 @@ end
 
 assign resetn = resetCnt == 4'd15;
 
-always@(posedge clock) begin
+always@(posedge clock or negedge resetn) begin
-  rstn_d <= resetn;
+  if(!resetn) begin
-	rst_n <= rstn_d;
+    timeout_rst_d1 <= 0;
+	  timeout_rst_d2 <= 0;
+	  timeout_rst_d3 <= 0;
+	  timeout_rst_d4 <= 0;
+	  timeout_rst_d5 <= 0;
+	  timeout_rst_d6 <= 0;
+	  timeout_rst_d7 <= 0;
+	  timeout_rst_d8 <= 0;
+  end else begin
+    timeout_rst_d1 <= timeout_rst;
+	  timeout_rst_d2 <= timeout_rst_d1;
+	  timeout_rst_d3 <= timeout_rst_d2;
+	  timeout_rst_d4 <= timeout_rst_d3;
+	  timeout_rst_d5 <= timeout_rst_d4;
+	  timeout_rst_d6 <= timeout_rst_d5;
+	  timeout_rst_d7 <= timeout_rst_d6;
+	  timeout_rst_d8 <= timeout_rst_d7;	
+  end
 end
 
+always @(posedge clock or negedge resetn) begin
+  if(!resetn) begin
+    resetn1 <= 1'b1;
+  end	else if((timeout_rst_d3 == 1'b0) && (timeout_rst_d2 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d4 == 1'b0) && (timeout_rst_d3 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d5 == 1'b0) && (timeout_rst_d4 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d6 == 1'b0) && (timeout_rst_d5 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d7 == 1'b0) && (timeout_rst_d6 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d8 == 1'b0) && (timeout_rst_d7 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else begin
+    resetn1 <= 1'b1;
+  end  
+end
+
+
+reg [5:0]  delay_io_last=6'b111111;
+reg [15:0] counter0=0;
+reg        clk_en0;
+wire       isLast_temp;
+wire       isLast_temp1;
+
+always @(posedge clk_10m_a or negedge resetn) begin
+  if(!resetn) begin
+    counter0 <= 16'd0;
+    clk_en0 <= 1'b0;
+  end	
+  else if(counter0 == 16'd9999) begin
+    counter0 <= 16'd0;
+    clk_en0 <= 1'b1;
+  end
+  else begin
+    counter0 <= counter0 + 1;
+    clk_en0 <= 1'b0;	 
+  end
+end
+
+
+always @(posedge clk_10m_a or negedge resetn) begin
+  if(!resetn) begin
+    delay_io_last <= 6'b111111;
+  end else if(clk_en0 == 1'b1) begin
+    delay_io_last[5:1] <= delay_io_last[4:0];
+    delay_io_last[0] <= isLast;
+  end
+end
+
+
+assign isLast_temp = &{!delay_io_last[5],!delay_io_last[4],!delay_io_last[3],!delay_io_last[2],!delay_io_last[1]};
+assign isLast_temp1 = ~isLast_temp;
+
 Gowin_PLLO Gowin_PLLO(
   .lock(lock_o), 
   .clkouta(clk_400m),
@@ -97,7 +180,7 @@ DHCEN dhcen_inst2 (
 //reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
 oser_rst u_oser_rst(
   .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
-  .rst_n(rst_n),
+  .rst_n(resetn && resetn1),
   .pll_lock(lock_o), // trigged by PLL Lock
   .reset_stop(reset_stop), // for DHCEN CE
   .reset_calib(reset_calib), // for IDES and CLKDIV reset
@@ -146,13 +229,14 @@ wire downstream_rx_cdr_err;
 wire upstream_rx_cdr_err;
 
 lvds_bus_slave_top i_lvds_bus_slave(
-  .rst_n(rst_n),
+  .rst_n(resetn && resetn1),
   .reset_calib(reset_calib),
   .oser_pclk(clk_10m_a),
   .oser_fclk(clk_50m_a),
   .ides_pclk(clk_100m_a),
   .ides_fclk(clk_400m_a),
-    
+  .timeout_rst(timeout_rst), //add 240523
+
   .lvds_down_din(lvds_down_din),
   .lvds_down_dout(lvds_down_dout),
   .lvds_up_din(lvds_up_din),
@@ -190,11 +274,11 @@ lvds_bus_slave_top i_lvds_bus_slave(
   );
 
 DIn16 i_din16(
-  .reset(~rst_n),
+  .reset(~resetn),
   .clock(clk_10m_a),
 
   .io_isOnline(isOnline),
-  .io_isLast(isLast),
+  .io_isLast(isLast_temp1),
   .io_DCIn(DCIn),
 
   .param_vendorID(`VENDORID),

src/main/verilog/do16_top.v

@@ -42,6 +42,16 @@ reg rst_n;
 reg rstn_d;
 
 wire resetn;
+reg  resetn1=1'b1;
+wire timeout_rst;
+reg timeout_rst_d1;
+reg timeout_rst_d2;
+reg timeout_rst_d3;
+reg timeout_rst_d4;
+reg timeout_rst_d5;
+reg timeout_rst_d6;
+reg timeout_rst_d7;
+reg timeout_rst_d8;
 
 reg [3:0] resetCnt = 4'd0;
 always @( posedge clock ) begin
@@ -52,11 +62,83 @@ end
 
 assign resetn = resetCnt == 4'd15;
 
-always@(posedge clock) begin
+always@(posedge clock or negedge resetn) begin
-  rstn_d <= resetn;
+  if(!resetn) begin
-	rst_n <= rstn_d;
+    timeout_rst_d1 <= 0;
+    timeout_rst_d2 <= 0;
+    timeout_rst_d3 <= 0;
+    timeout_rst_d4 <= 0;
+    timeout_rst_d5 <= 0;
+    timeout_rst_d6 <= 0;
+    timeout_rst_d7 <= 0;
+    timeout_rst_d8 <= 0;
+  end
+	else begin
+    timeout_rst_d1 <= timeout_rst;
+    timeout_rst_d2 <= timeout_rst_d1;
+    timeout_rst_d3 <= timeout_rst_d2;
+    timeout_rst_d4 <= timeout_rst_d3;
+    timeout_rst_d5 <= timeout_rst_d4;
+    timeout_rst_d6 <= timeout_rst_d5;
+    timeout_rst_d7 <= timeout_rst_d6;
+    timeout_rst_d8 <= timeout_rst_d7;	
+  end
 end
 
+always @(posedge clock or negedge resetn) begin
+  if(!resetn) begin
+    resetn1 <= 1'b1;
+  end else if((timeout_rst_d3 == 1'b0) && (timeout_rst_d2 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d4 == 1'b0) && (timeout_rst_d3 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d5 == 1'b0) && (timeout_rst_d4 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d6 == 1'b0) && (timeout_rst_d5 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d7 == 1'b0) && (timeout_rst_d6 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else if((timeout_rst_d8 == 1'b0) && (timeout_rst_d7 == 1'b1)) begin
+    resetn1 <= 1'b0;
+  end else begin
+    resetn1 <= 1'b1;
+  end
+end
+
+
+reg [5:0]  delay_io_last=6'b111111;
+reg [15:0] counter0=0;
+reg        clk_en0;
+wire       isLast_temp;
+wire       isLast_temp1;
+
+always @(posedge clk_10m_a or negedge resetn) begin
+  if(!resetn) begin
+    counter0 <= 16'd0;
+    clk_en0 <= 1'b0;
+  end	else if(counter0 == 16'd9999) begin
+    counter0 <= 16'd0;
+    clk_en0 <= 1'b1;
+  end else begin
+    counter0 <= counter0 + 1;
+    clk_en0 <= 1'b0;	 
+  end
+end
+
+
+always @(posedge clk_10m_a or negedge resetn) begin
+  if(!resetn) begin
+    delay_io_last <= 6'b111111;
+  end else if(clk_en0 == 1'b1) begin
+    delay_io_last[5:1] <= delay_io_last[4:0];
+    delay_io_last[0] <= isLast;
+  end
+end
+
+
+assign isLast_temp = &{!delay_io_last[5],!delay_io_last[4],!delay_io_last[3],!delay_io_last[2],!delay_io_last[1]};
+assign isLast_temp1 = ~isLast_temp;
+
 Gowin_PLLO Gowin_PLLO(
   .lock(lock_o), 
   .clkouta(clk_400m),
@@ -103,7 +185,7 @@ DHCEN dhcen_inst2 (
 //reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
 oser_rst u_oser_rst(
   .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
-  .rst_n(rst_n),
+  .rst_n(resetn && resetn1),
   .pll_lock(lock_o), // trigged by PLL Lock
   .reset_stop(reset_stop), // for DHCEN CE
   .reset_calib(reset_calib), // for IDES and CLKDIV reset
@@ -152,12 +234,13 @@ wire downstream_rx_cdr_err;
 wire upstream_rx_cdr_err;
 
 lvds_bus_slave_top i_lvds_bus_slave(
-  .rst_n(rst_n),
+  .rst_n(resetn && resetn1),
   .reset_calib(reset_calib),
   .oser_pclk(clk_10m_a),
   .oser_fclk(clk_50m_a),
   .ides_pclk(clk_100m_a),
   .ides_fclk(clk_400m_a),
+  .timeout_rst(timeout_rst), //add 240523
 
   .lvds_down_din(lvds_down_din),
   .lvds_down_dout(lvds_down_dout),
@@ -197,11 +280,11 @@ lvds_bus_slave_top i_lvds_bus_slave(
 
 
 DOut16 i_dout16(
-  .reset(~rst_n),
+  .reset(~resetn),
   .clock(clk_10m_a),
 
   .io_isOnline(isOnline),
-  .io_isLast(isLast),
+  .io_isLast(isLast_temp1),
   .io_DCIn(DCIn),
 
   .param_vendorID(`VENDORID),

src/test/scala/gcd/test.scala

@@ -13,7 +13,7 @@ import org.chipsalliance.cde.config._
 
 
 object testModule extends App {
-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => { new BackBoardMst }),
     ))
 
@@ -21,11 +21,11 @@ object testModule extends App {
   //     ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
   //   ))
 
-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => { new DIn16 })
     ))
 
-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => { new DOut16 })
     ))
   // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(