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临时解决方案

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RuigeLee
2024-05-24 17:31:49 +08:00
parent 7f85f14d92
commit b5fb27ab7c
5 changed files with 205 additions and 27 deletions
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6
src/test/scala/gcd/test.scala
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@@ -13,7 +13,7 @@ import org.chipsalliance.cde.config._
object testModule extends App {
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new BackBoardMst }),
))
@@ -21,11 +21,11 @@ object testModule extends App {
// ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new DIn16 })
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new DOut16 })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(