临时解决方案

Makefile

@@ -12,13 +12,13 @@ compile:
 # 	sbt "test:runMain test.testModule"
 
 back:
-	rm -f ./generated/*
+	rm -f ./generated/back/*
 	sbt "test:runMain test.testModule"
-	cp ./src/main/verilog/backBoardMstTop.v ./generated/
-	cp ./src/main/verilog/oser_rst.v ./generated/
-	cp ./src/main/verilog/di16_top.v ./generated/
-	cp ./src/main/verilog/do16_top.v ./generated/
-	cp ./src/main/verilog/defineParam.v ./generated/
+	cp ./src/main/verilog/backBoardMstTop.v ./generated/back/
+	cp ./src/main/verilog/oser_rst.v ./generated/back/
+	cp ./src/main/verilog/di16_top.v ./generated/back/
+	cp ./src/main/verilog/do16_top.v ./generated/back/
+	cp ./src/main/verilog/defineParam.v ./generated/back/