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尝试速率配平，回环改到phy上

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This commit is contained in:
Ruige Lee
2025-05-07 18:12:01 +08:00
parent 19f4140dec
commit b55deb239f
6 changed files with 63 additions and 58 deletions
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8
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -114,7 +114,7 @@ trait CDRInAxis{ this: CDRInBase =>
val shiftData = Dualb4b5Decoder(checkSFD(9,0))
val payloadLen = Reg(UInt(12.W))
val payloadLen = RegInit(0.U(12.W))
when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
payloadLen := Cat( shiftData, 0.U(4.W) )
} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
@@ -149,8 +149,8 @@ trait CDRInAxis{ this: CDRInBase =>
byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
assert( byteCnt <= (HeaderByte-1).U )
} .elsewhen( stateCurr === STATE_PAYLOAD ){
byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U )
assert( byteCnt <= ( payloadLen-1.U ) )
byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
assert( byteCnt <= ( payloadLen+ (4-1).U ) )
}
}
@@ -161,7 +161,7 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tuser = false.B
val axis_tlast = RegNext( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), false.B )
val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B )
io.axis.valid := axis_valid
io.axis.bits.tdata := axis_tdata