切换大块SRAM

This commit is contained in:
RuigeLee
2024-11-04 17:38:51 +08:00
parent 7754f6b64e
commit b1c71b67a0
2 changed files with 37 additions and 47 deletions

View File

@@ -15,22 +15,22 @@ class SimpleSRAM()(implicit p: Parameters) extends BackModule{
val io: SimpleSRAMIO = IO(new SimpleSRAMIO)
val mem = SyncReadMem(1024, Vec(4, UInt(8.W)))
val mem = SyncReadMem(1024, UInt(32.W))
io.mem.rdata := DontCare
// when(io.mem.valid) {
mem.write(
io.mem.addr(11,2),
VecInit( io.mem.wdata(31,24), io.mem.wdata(23,16), io.mem.wdata(15,8), io.mem.wdata(7,0) ),
VecInit( io.mem.valid & io.mem.wstrb.extract(3), io.mem.valid & io.mem.wstrb.extract(2), io.mem.valid & io.mem.wstrb.extract(1), io.mem.valid & io.mem.wstrb.extract(0) )
)
when( io.mem.valid & io.mem.wstrb.extract(0) ){
mem.write( io.mem.addr(11,2), io.mem.wdata )
assert( io.mem.wstrb.extract(1) & io.mem.wstrb.extract(2) & io.mem.wstrb.extract(3) )
}
io.mem.rdata := Cat( mem.read(io.mem.addr(11,2), true.B).reverse )
io.mem.rdata := mem.read(io.mem.addr(11,2), true.B)
// when ( io.mem.wstrb =/= 0.U ) {