diff --git a/src/main/scala/backBoard/pico/SimpleSRAM.scala b/src/main/scala/backBoard/pico/SimpleSRAM.scala
index 958d898..f661b27 100644
--- a/src/main/scala/backBoard/pico/SimpleSRAM.scala
+++ b/src/main/scala/backBoard/pico/SimpleSRAM.scala
@@ -15,22 +15,22 @@ class SimpleSRAM()(implicit p: Parameters) extends BackModule{
 
   val io: SimpleSRAMIO = IO(new SimpleSRAMIO)
 
-  val mem = SyncReadMem(1024, Vec(4, UInt(8.W)))
+  val mem = SyncReadMem(1024, UInt(32.W))
 
 
   io.mem.rdata := DontCare
 
   // when(io.mem.valid) {
 
-    mem.write(
-      io.mem.addr(11,2),
-      VecInit( io.mem.wdata(31,24), io.mem.wdata(23,16), io.mem.wdata(15,8), io.mem.wdata(7,0) ),
-      VecInit( io.mem.valid & io.mem.wstrb.extract(3), io.mem.valid & io.mem.wstrb.extract(2), io.mem.valid & io.mem.wstrb.extract(1), io.mem.valid & io.mem.wstrb.extract(0) )
-    )
+  when( io.mem.valid & io.mem.wstrb.extract(0) ){
+    mem.write( io.mem.addr(11,2), io.mem.wdata )
 
+    assert( io.mem.wstrb.extract(1) & io.mem.wstrb.extract(2) & io.mem.wstrb.extract(3) )
+  }
 
-    io.mem.rdata := Cat( mem.read(io.mem.addr(11,2), true.B).reverse )
+  io.mem.rdata := mem.read(io.mem.addr(11,2), true.B)
 
+  
 
 
     // when ( io.mem.wstrb =/= 0.U ) {
diff --git a/tb/backSys_tb.v b/tb/backSys_tb.v
index 03c0f1f..9f9b74a 100644
--- a/tb/backSys_tb.v
+++ b/tb/backSys_tb.v
@@ -119,10 +119,8 @@ initial begin
 end
 
 
-	`define SRAM0 s_Mst.sram.mem_0.mem_0_ext.ram
-	`define SRAM1 s_Mst.sram.mem_1.mem_0_ext.ram
-	`define SRAM2 s_Mst.sram.mem_2.mem_0_ext.ram
-	`define SRAM3 s_Mst.sram.mem_3.mem_0_ext.ram
+	`define SRAM s_Mst.sram.mem.mem_ext.ram
+
 
 
 	localparam DP = 2**14;
@@ -132,32 +130,24 @@ end
 		initial begin
 			$readmemh("./tb/sw/build/mstTest.verilog", mem);
 			for ( i = 0; i < DP; i = i + 1 ) begin
-				`SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
-				`SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
-				`SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
-				`SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
+				`SRAM[i][7:0]   = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
+				`SRAM[i][15:8]  = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
+				`SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
+				`SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
 
 				// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
 			end
 		end 
 
 
-	`define SLV0_SRAM0 s_Slv0.sram.mem_0.mem_0_ext.ram
-	`define SLV0_SRAM1 s_Slv0.sram.mem_1.mem_0_ext.ram
-	`define SLV0_SRAM2 s_Slv0.sram.mem_2.mem_0_ext.ram
-	`define SLV0_SRAM3 s_Slv0.sram.mem_3.mem_0_ext.ram
-	`define SLV1_SRAM0 s_Slv1.sram.mem_0.mem_0_ext.ram
-	`define SLV1_SRAM1 s_Slv1.sram.mem_1.mem_0_ext.ram
-	`define SLV1_SRAM2 s_Slv1.sram.mem_2.mem_0_ext.ram
-	`define SLV1_SRAM3 s_Slv1.sram.mem_3.mem_0_ext.ram
-	`define SLV2_SRAM0 s_Slv2.sram.mem_0.mem_0_ext.ram
-	`define SLV2_SRAM1 s_Slv2.sram.mem_1.mem_0_ext.ram
-	`define SLV2_SRAM2 s_Slv2.sram.mem_2.mem_0_ext.ram
-	`define SLV2_SRAM3 s_Slv2.sram.mem_3.mem_0_ext.ram
-	`define SLV3_SRAM0 s_Slv3.sram.mem_0.mem_0_ext.ram
-	`define SLV3_SRAM1 s_Slv3.sram.mem_1.mem_0_ext.ram
-	`define SLV3_SRAM2 s_Slv3.sram.mem_2.mem_0_ext.ram
-	`define SLV3_SRAM3 s_Slv3.sram.mem_3.mem_0_ext.ram
+	`define SLV0_SRAM s_Slv0.sram.mem.mem_ext.ram
+
+	`define SLV1_SRAM s_Slv1.sram.mem.mem_ext.ram
+
+	`define SLV2_SRAM s_Slv2.sram.mem.mem_ext.ram
+
+	`define SLV3_SRAM s_Slv3.sram.mem.mem_ext.ram
+
 
 	localparam DPS = 2**14;
 
@@ -165,25 +155,25 @@ end
 		initial begin
 			$readmemh("./tb/sw/build/slvTest.verilog", mem);
 			for ( i = 0; i < DP; i = i + 1 ) begin
-				`SLV0_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
-				`SLV0_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
-				`SLV0_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
-				`SLV0_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
+				`SLV0_SRAM[i][7:0]   = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
+				`SLV0_SRAM[i][15:8]  = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
+				`SLV0_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
+				`SLV0_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
 
-				`SLV1_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
-				`SLV1_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
-				`SLV1_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
-				`SLV1_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
+				`SLV1_SRAM[i][7:0]   = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
+				`SLV1_SRAM[i][15:8]  = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
+				`SLV1_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
+				`SLV1_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
 
-				`SLV2_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
-				`SLV2_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
-				`SLV2_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
-				`SLV2_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
+				`SLV2_SRAM[i][7:0]   = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
+				`SLV2_SRAM[i][15:8]  = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
+				`SLV2_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
+				`SLV2_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
 
-				`SLV3_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
-				`SLV3_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
-				`SLV3_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
-				`SLV3_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
+				`SLV3_SRAM[i][7:0]   = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
+				`SLV3_SRAM[i][15:8]  = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
+				`SLV3_SRAM[i][23:16] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
+				`SLV3_SRAM[i][31:24] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
 				// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
 			end
 		end