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重新排地址空间，不要高地址

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RuigeLee
2024-10-31 18:02:29 +08:00
parent 46882b6b4d
commit b13a3b8aad
1 changed files with 12 additions and 10 deletions
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22
src/main/scala/backBoard/pico/BackSystem.scala
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@@ -53,9 +53,18 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
))
)))
val sram = LazyModule(new TLRAM(
address = AddressSet(0x00000000L, 0xfffL),
cacheable = false,
executable = true,
atomics = false,
beatBytes = 4,
sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
))
val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0x40000000L, 0xffL)),
address = Seq(AddressSet(0x00001000L, 0xffL)),
regionType = RegionType.UNCACHED,
executable = false,
supportsGet = TransferSizes(32/8, 32/8),
@@ -64,14 +73,7 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
)),
beatBytes = 32/8)))
val sram = LazyModule(new TLRAM(
address = AddressSet(0x80000000L, 0xfffL),
cacheable = false,
executable = true,
atomics = false,
beatBytes = 4,
sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
))
// val uart = LazyModule( new TLUART(
@@ -83,7 +85,7 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
val gpioNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0x60000000L, 0xffL)),
address = Seq(AddressSet(0x0002000L, 0xffL)),
regionType = RegionType.UNCACHED,
executable = false,
supportsGet = TransferSizes(32/8, 32/8),