From b13a3b8aad8d5107ca4fee858251ea2e266738b5 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 31 Oct 2024 18:02:29 +0800 Subject: [PATCH] =?UTF-8?q?=E9=87=8D=E6=96=B0=E6=8E=92=E5=9C=B0=E5=9D=80?= =?UTF-8?q?=E7=A9=BA=E9=97=B4=EF=BC=8C=E4=B8=8D=E8=A6=81=E9=AB=98=E5=9C=B0?= =?UTF-8?q?=E5=9D=80?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/pico/BackSystem.scala | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala index 6503872..8319553 100644 --- a/src/main/scala/backBoard/pico/BackSystem.scala +++ b/src/main/scala/backBoard/pico/BackSystem.scala @@ -53,9 +53,18 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter )) ))) + val sram = LazyModule(new TLRAM( + address = AddressSet(0x00000000L, 0xfffL), + cacheable = false, + executable = true, + atomics = false, + beatBytes = 4, + sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response + )) + val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1( managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0x40000000L, 0xffL)), + address = Seq(AddressSet(0x00001000L, 0xffL)), regionType = RegionType.UNCACHED, executable = false, supportsGet = TransferSizes(32/8, 32/8), @@ -64,14 +73,7 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter )), beatBytes = 32/8))) - val sram = LazyModule(new TLRAM( - address = AddressSet(0x80000000L, 0xfffL), - cacheable = false, - executable = true, - atomics = false, - beatBytes = 4, - sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response - )) + // val uart = LazyModule( new TLUART( @@ -83,7 +85,7 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter val gpioNode = TLManagerNode(Seq(TLSlavePortParameters.v1( managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0x60000000L, 0xffL)), + address = Seq(AddressSet(0x0002000L, 0xffL)), regionType = RegionType.UNCACHED, executable = false, supportsGet = TransferSizes(32/8, 32/8),