ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

test pass

Browse Source
This commit is contained in:
RuigeLee
2023-09-14 19:16:17 +08:00
parent 6fd836fc9c
commit b098ca963e
6 changed files with 466 additions and 255 deletions
Download Patch File Download Diff File Expand all files Collapse all files

117
src/main/verilog/oser_rst.v Normal file
View File

@@ -0,0 +1,117 @@
module oser_rst
(input clk_in, //!system clock or any other speed comparable with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
input rst_n, //!from system reset
input pll_lock, //!RX PLL lock flag
output reg reset_stop, //!to DHCEN CE port
output reg reset_calib, //!to IDES/CLKDIV reset port
output reg set_calib, //!not used
output reg ready //!ready
);
/*******************************************************************************
* OSER FSM States defined
*******************************************************************************/
parameter STATE_IDLE = 5'b0000;
parameter STATE_SERDES_STOP_S = 5'b0001;
parameter STATE_SERDES_RST_S = 5'b0010;
parameter STATE_SERDES_RST_E = 5'b0011;
parameter STATE_SERDES_STOP_E = 5'b0100;
parameter STATE_SERDES_WAIT = 5'b0101;
parameter STATE_SERDES_CALIB = 5'b0110;
parameter STATE_SERDES_READY = 5'b0111;
/*******************************************************************************
//reg and wire definition
*******************************************************************************/
reg [4:0] Fsm_serdes_rst_ctrl;
reg [9:0] Cnt_serdes_rst_ctrl;
/*******************************************************************************/
/*******************************************************************************/
always @(posedge clk_in or negedge rst_n)
begin
if (~rst_n) begin
Fsm_serdes_rst_ctrl <= STATE_IDLE;
Cnt_serdes_rst_ctrl <= 'd0;
reset_stop <= 1'b0;
reset_calib <= 1'b0;
set_calib <= 1'b0;
ready <= 1'b0;
end
else begin
case(Fsm_serdes_rst_ctrl)
STATE_IDLE:begin//idle
if(pll_lock)
Fsm_serdes_rst_ctrl <= STATE_SERDES_STOP_S;
Cnt_serdes_rst_ctrl <= 'd0;
reset_stop <= 1'b0;
reset_calib <= 1'b0;
set_calib <= 1'b0;
ready <= 1'b0;
end
STATE_SERDES_STOP_S:begin
Cnt_serdes_rst_ctrl<=Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[3])begin
// reset_stop <= 1'b1;//
reset_calib <= 1'b1;//
Fsm_serdes_rst_ctrl <= STATE_SERDES_RST_S;
end
else begin
reset_stop <= 1'b0;
end
end
STATE_SERDES_RST_S:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[5])begin
// reset_calib <= 1'b1;
reset_stop <= 1'b1;
Fsm_serdes_rst_ctrl <= STATE_SERDES_RST_E;
end
end
STATE_SERDES_RST_E:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[6])begin
reset_calib <= 1'b0;
Fsm_serdes_rst_ctrl <= STATE_SERDES_STOP_E;
end
end
STATE_SERDES_STOP_E:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[7])begin
reset_stop <= 1'b0;
Fsm_serdes_rst_ctrl <= STATE_SERDES_CALIB;
end
end
STATE_SERDES_CALIB:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[3:0] == 4'h04 )begin
set_calib <= 1'b1;
end
// if(Cnt_serdes_rst_ctrl[3:0] == 4'h08)begin
// set_calib <= 1'b0;
// end
if(Cnt_serdes_rst_ctrl[6])begin
set_calib <= 1'b0;
Fsm_serdes_rst_ctrl <= STATE_SERDES_READY;
end
end
STATE_SERDES_READY:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[8])begin
ready <= 1'b1;
// set_calib <= 1'b0;
Fsm_serdes_rst_ctrl <= STATE_SERDES_WAIT;
end
end
STATE_SERDES_WAIT:begin
if(~pll_lock)begin
Fsm_serdes_rst_ctrl<=STATE_IDLE;
end
end
default:begin
Fsm_serdes_rst_ctrl<=STATE_IDLE;
end
endcase
end
end
endmodule