From b098ca963e144fe707e752a96f630dc58b765e1d Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 14 Sep 2023 19:16:17 +0800 Subject: [PATCH] test pass --- src/main/scala/backBoard/BackBoardMst.scala | 316 +++++++++++--------- src/main/scala/backBoard/BackBoardSlv.scala | 8 +- src/main/scala/backBoard/goWinBus.scala | 44 +-- src/main/verilog/backBoardMstTop.v | 102 ++++--- src/main/verilog/backBoardSlvTop.v | 134 ++++++--- src/main/verilog/oser_rst.v | 117 ++++++++ 6 files changed, 466 insertions(+), 255 deletions(-) create mode 100644 src/main/verilog/oser_rst.v diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index 3fd1c25..a44e71a 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -95,6 +95,11 @@ class BackBoardMstBase extends Module{ //10M mirrorUp.io.clockw := io.oser_pclk.asBool mirrorUp.io.clockr := io.oser_pclk.asBool + + io.cdrErr := statusCDRErr + io.crcErr := statusCRCErr + io.linkErr := statusLinkErr + } @@ -144,10 +149,10 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase => ( activeAddr === 1.U) -> Cat( ctrlTransmit, - ctrlCDRErr , - ctrlCRCErr , - ctrlLinkErr , - ctrlSynch , + 0.U(1.W), + 0.U(1.W), + 0.U(1.W), + ctrlSynch, ctrlInit ), ( activeAddr === 2.U) -> slvNum, @@ -162,9 +167,17 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase => when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 1.U) ){ ctrlTransmit := fsmcdataInSync.extract(5) - ctrlCDRErr := fsmcdataInSync.extract(4) - ctrlCRCErr := fsmcdataInSync.extract(3) - ctrlLinkErr := fsmcdataInSync.extract(2) + + when( fsmcdataInSync.extract(4) ){ + statusCDRErr := false.B + } + when( fsmcdataInSync.extract(3) ){ + statusCRCErr := false.B + } + when( fsmcdataInSync.extract(2) ){ + statusLinkErr := false.B + } + ctrlSynch := fsmcdataInSync.extract(1) ctrlInit := fsmcdataInSync.extract(0) } @@ -202,135 +215,139 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase => val ( _, isInitTimeout ) = Counter(Range( 0,5200), ctrlInit, isInitCntReset) val synchCnt = Reg(UInt(3.W)) - when( isInitTimeout ){ - stateCur := 0.U + when(ctrlInit){ + when( isInitTimeout ){ - frame_info_update_en := false.B - slave_type_num := 0.U - slave_data_length := 0.U + stateCur := 0.U - tx_start := false.B - - } .elsewhen( stateCur === 0.U ){ - stateCur := 1.U + frame_info_update_en := false.B + slave_type_num := 0.U + slave_data_length := 0.U - frame_info_update_en := true.B - slave_type_num := Cat( "b00".U(2.W), slvNum ) - slave_data_length := ((8/8)*16-1).U + tx_start := false.B + + } .elsewhen( stateCur === 0.U ){ + stateCur := 1.U - tx_start := false.B - } .elsewhen( stateCur === 1.U ){ // tx start - stateCur := 2.U + frame_info_update_en := true.B + slave_type_num := Cat( "b00".U(2.W), slvNum ) + slave_data_length := ((8/8)*16-1).U - frame_info_update_en := false.B - tx_start := true.B + tx_start := false.B + } .elsewhen( stateCur === 1.U ){ // tx start + stateCur := 2.U - } .elsewhen( stateCur === 2.U ){ + frame_info_update_en := false.B + tx_start := true.B - tx_start := false.B + } .elsewhen( stateCur === 2.U ){ - when( lvdsMst.io.slave_link_num_valid ){ - slvNum := lvdsMst.io.slave_link_num(5,0) - stateCur := 3.U - } + tx_start := false.B - } .elsewhen( stateCur === 3.U ){ - frame_info_update_en := false.B - slave_type_num := 0.U - slave_data_length := 0.U - - tx_start := false.B - - stateCur := 4.U - - } .elsewhen( stateCur === 4.U ){ - stateCur := 5.U - - frame_info_update_en := true.B - slave_type_num := Cat( "b00".U(2.W), slvNum ) - slave_data_length := ((8/8)*16-1).U - - tx_start := false.B - } .elsewhen( stateCur === 5.U ){ // tx start - stateCur := 6.U - - frame_info_update_en := false.B - tx_start := true.B - - } .elsewhen( stateCur === 6.U ){ - - tx_start := false.B - - when( lvdsMst.io.slave_link_num_valid ){ - when( slvNum === lvdsMst.io.slave_link_num(5,0) ){ - stateCur := 7.U - } .otherwise{ - printf("Initialization failed, waitting for timeout!\n") + when( lvdsMst.io.slave_link_num_valid ){ + slvNum := lvdsMst.io.slave_link_num - 1.U + stateCur := 3.U } - } - } .elsewhen( stateCur === 7.U ){ - when( ctrlSynch ){ - stateCur := 8.U - synchCnt := 0.U - } .otherwise{ + } .elsewhen( stateCur === 3.U ){ + frame_info_update_en := false.B + slave_type_num := 0.U + slave_data_length := 0.U + + tx_start := false.B + + stateCur := 4.U + + } .elsewhen( stateCur === 4.U ){ + stateCur := 5.U + + frame_info_update_en := true.B + slave_type_num := Cat( "b00".U(2.W), slvNum ) + slave_data_length := ((8/8)*16-1).U + + tx_start := false.B + } .elsewhen( stateCur === 5.U ){ // tx start + stateCur := 6.U + + frame_info_update_en := false.B + tx_start := true.B + + } .elsewhen( stateCur === 6.U ){ + + tx_start := false.B + + when( lvdsMst.io.slave_link_num_valid ){ + when( slvNum === lvdsMst.io.slave_link_num - 1.U ){ + stateCur := 7.U + } .otherwise{ + printf("Initialization failed, waitting for timeout!\n") + } + } + + } .elsewhen( stateCur === 7.U ){ + when( ctrlSynch ){ + stateCur := 8.U + synchCnt := 0.U + } .otherwise{ + statusInit := true.B + ctrlInit := false.B + } + + } .elsewhen( stateCur === 8.U ){ //synch + frame_info_update_en := false.B + slave_type_num := 0.U + slave_data_length := 0.U + + tx_start := false.B + + stateCur := 9.U + + } .elsewhen( stateCur === 9.U ){ + stateCur := 10.U + + frame_info_update_en := true.B + slave_type_num := Cat( "b01".U(2.W), slvNum ) + slave_data_length := ((8/8)*16-1).U + + tx_start := false.B + } .elsewhen( stateCur === 10.U ){ // tx start + stateCur := 11.U + + frame_info_update_en := false.B + tx_start := true.B + + } .elsewhen( stateCur === 11.U ){ + + tx_start := false.B + + when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ + stateCur := 12.U + synchCnt := synchCnt + 1.U + } + + } .elsewhen( stateCur === 12.U ){ + when( synchCnt === 4.U ){ + stateCur := 13.U + } .otherwise{ + stateCur := 8.U + } + } .elsewhen( stateCur === 13.U ){ + statusSynch := true.B statusInit := true.B + ctrlSynch := false.B ctrlInit := false.B + + } .elsewhen( stateCur === 15.U ){ + } + .otherwise{ - } .elsewhen( stateCur === 8.U ){ //synch - frame_info_update_en := false.B - slave_type_num := 0.U - slave_data_length := 0.U - - tx_start := false.B - - stateCur := 9.U - - } .elsewhen( stateCur === 9.U ){ - stateCur := 10.U - - frame_info_update_en := true.B - slave_type_num := Cat( "b01".U(2.W), slvNum ) - slave_data_length := ((8/8)*16-1).U - - tx_start := false.B - } .elsewhen( stateCur === 10.U ){ // tx start - stateCur := 11.U - - frame_info_update_en := false.B - tx_start := true.B - - } .elsewhen( stateCur === 11.U ){ - - tx_start := false.B - - when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ - stateCur := 12.U - synchCnt := synchCnt + 1.U } - - } .elsewhen( stateCur === 12.U ){ - when( synchCnt === 4.U ){ - stateCur := 13.U - } .otherwise{ - stateCur := 8.U - } - } .elsewhen( stateCur === 12.U ){ - statusSynch := true.B - statusInit := true.B - ctrlSynch := false.B - ctrlInit := false.B - - } .elsewhen( stateCur === 15.U ){ - - } - .otherwise{ - assert(false.B) } + } @@ -340,67 +357,68 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase => val ( _, trigger ) = Counter(Range( 0,1000), ctrlTransmit ) + when(ctrlTransmit){ + when( trigger ){ //reset + stateCur := 0.U - when( trigger ){ //reset - stateCur := 0.U + frame_info_update_en := false.B + slave_type_num := 0.U + slave_data_length := 0.U - frame_info_update_en := false.B - slave_type_num := 0.U - slave_data_length := 0.U + tx_start := false.B + - tx_start := false.B - + } .elsewhen( stateCur === 0.U ){ //setting + stateCur := 1.U - } .elsewhen( stateCur === 0.U ){ //setting - stateCur := 1.U + frame_info_update_en := true.B + slave_type_num := Cat( "b10".U(2.W), slvNum ) + slave_data_length := ((8/8)*16-1).U - frame_info_update_en := true.B - slave_type_num := Cat( "b10".U(2.W), slvNum ) - slave_data_length := ((8/8)*16-1).U + tx_start := false.B + } .elsewhen( stateCur === 1.U ){ // tx start + stateCur := 2.U - tx_start := false.B - } .elsewhen( stateCur === 1.U ){ // tx start - stateCur := 2.U + frame_info_update_en := false.B + tx_start := true.B - frame_info_update_en := false.B - tx_start := true.B + } .elsewhen( stateCur === 2.U ){ //waiting for busy drop - } .elsewhen( stateCur === 2.U ){ //waiting for busy drop + tx_start := false.B - tx_start := false.B + when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ + stateCur := 3.U + } + + } .elsewhen( stateCur === 3.U ){ + + } .otherwise{ - when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ - stateCur := 3.U } - - } .elsewhen( stateCur === 3.U ){ - - } .otherwise{ - - assert(false.B) } + val addrr = RegInit(0.U(10.W)) val addrw = RegInit(0.U(10.W)) when( trigger ){ addrw := 0.U - } .elsewhen( lvdsMst.io.rx_data_valid & ~isSync){ + } .elsewhen( lvdsMst.io.rx_data_valid & ctrlTransmit){ assert( (stateCur === 2.U) || (stateCur === 3.U) ) addrw := addrw + 1.U } when( trigger ){ addrr := 0.U - } .elsewhen( lvdsMst.io.tx_data_ready & ~isSync){ + } .elsewhen( lvdsMst.io.tx_data_ready & ctrlTransmit){ addrr := addrr + 1.U } - mirrorDown.io.enr := (stateCur === 1.U || stateCur === 2.U) & ~isSync + mirrorDown.io.enr := (stateCur === 1.U || stateCur === 2.U) & ctrlTransmit lvdsMst.io.tx_data_in := mirrorDown.io.datar mirrorDown.io.addrr := addrr - mirrorUp.io.enw := lvdsMst.io.rx_data_valid & ~isSync + mirrorUp.io.enw := lvdsMst.io.rx_data_valid & ctrlTransmit mirrorUp.io.dataw := lvdsMst.io.rx_data_out mirrorUp.io.addrw := addrw @@ -409,7 +427,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase => trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase => when( lvdsMst.io.closed_loop_err ){ slvOffLine := lvdsMst.io.link_err_location(5,0) - statuslinkErr := true.B + statusLinkErr := true.B statusSynch := false.B statusInit := false.B } @@ -419,7 +437,7 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase => ctrlTransmit := false.B } - when( lvdsMst.io.upstream_crc_valid & upstream_crc_err ){ + when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){ statusCRCErr := true.B ctrlTransmit := false.B } diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala index 6e7888b..4945ead 100644 --- a/src/main/scala/backBoard/BackBoardSlv.scala +++ b/src/main/scala/backBoard/BackBoardSlv.scala @@ -59,7 +59,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase => } when( lvdsSlv.io.downstream_rx_crc_valid ){ - when( ~downstream_rx_crc_err ){ + when( ~lvdsSlv.io.downstream_rx_crc_err ){ downReg := downRegTemp } } @@ -86,7 +86,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase => trait BackBoardSlvUp{ this: BackBoardSlvBase => - val upCnt = RegInit(31.U(6.W)) + val upCnt = RegInit(15.U(6.W)) val upTimeoutEn = RegInit( false.B ) val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready) val ( _, upTimeout ) = Counter( Range( 0,1000 ), upTimeoutEn, upTimeoutRst ) @@ -98,7 +98,7 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase => when( upTimeout ){ upTimeoutEn := false.B - } .elsewhen( upCnt === 31.U ){ + } .elsewhen( upCnt === 15.U ){ upTimeoutEn := false.B } .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){ upTimeoutEn := true.B @@ -107,7 +107,7 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase => when( upTimeout ){ upCnt := 0.U }.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){ - when(upCnt === 31.U){ + when(upCnt === 15.U){ upCnt := 0.U } .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){ upCnt := upCnt + 1.U diff --git a/src/main/scala/backBoard/goWinBus.scala b/src/main/scala/backBoard/goWinBus.scala index a7e7365..099bb5b 100644 --- a/src/main/scala/backBoard/goWinBus.scala +++ b/src/main/scala/backBoard/goWinBus.scala @@ -86,15 +86,15 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline { | output [7:0] upstream_crc_err_count, | output upstream_cdr_err, | - | output closed_loop_err(closed_loop_err), - | output [6:0] link_err_location(link_err_location), + | output closed_loop_err, + | output [6:0] link_err_location, | - | output test_downstream_tx_en(test_downstream_tx_en), - | output [7:0] test_downstream_tx_8b_data(test_downstream_tx_8b_data), - | output [9:0] test_downstream_tx_10b_data(test_downstream_tx_10b_data), - | output test_upstream_rx_busy(test_upstream_rx_busy), - | output [9:0] test_upstream_rx_10b_data(test_upstream_rx_10b_data), - | output [7:0] test_upstream_rx_8b_data(test_upstream_rx_8b_data) + | output test_downstream_tx_en, + | output [7:0] test_downstream_tx_8b_data, + | output [9:0] test_downstream_tx_10b_data, + | output test_upstream_rx_busy, + | output [9:0] test_upstream_rx_10b_data, + | output [7:0] test_upstream_rx_8b_data | ); | | lvds_bus_master_top i_lvds_bus_master( @@ -124,7 +124,7 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline { | .upstream_crc_valid(upstream_crc_valid), //output | .upstream_crc_err(upstream_crc_err), //output | .upstream_crc_err_count(upstream_crc_err_count), //output [7:0] - | .upstream_cdr_err(upstream_cdr_err) //output + | .upstream_cdr_err(upstream_cdr_err), //output | | .closed_loop_err(closed_loop_err), //output | .link_err_location(link_err_location), //output [6:0] @@ -233,19 +233,19 @@ class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline { | output [7:0] upstream_rx_crc_err_counter, | output upstream_rx_cdr_err, | - | output [6:0] local_slave_id(local_slave_id), - | output [9:0] test_downstream_rx_10b_data(test_downstream_rx_10b_data), - | output [7:0] test_downstream_rx_8b_data(test_downstream_rx_8b_data), - | output [3:0] test_downstream_rx_state_machine(test_downstream_rx_state_machine), - | output test_downstream_tx_en(test_downstream_tx_en), - | output [7:0] test_downstream_tx_8b_data(test_downstream_tx_8b_data), - | output [9:0] test_downstream_tx_10b_data(test_downstream_tx_10b_data), - | output [9:0] test_upstream_rx_10b_data(test_upstream_rx_10b_data), - | output [7:0] test_upstream_rx_8b_data(test_upstream_rx_8b_data), - | output [3:0] test_upstream_rx_state_machine(test_upstream_rx_state_machine), - | output test_upstream_tx_en(test_upstream_tx_en), - | output [7:0] test_upstream_tx_8b_data(test_upstream_tx_8b_data), - | output [9:0] test_upstream_tx_10b_data(test_upstream_tx_10b_data) + | output [6:0] local_slave_id, + | output [9:0] test_downstream_rx_10b_data, + | output [7:0] test_downstream_rx_8b_data, + | output [3:0] test_downstream_rx_state_machine, + | output test_downstream_tx_en, + | output [7:0] test_downstream_tx_8b_data, + | output [9:0] test_downstream_tx_10b_data, + | output [9:0] test_upstream_rx_10b_data, + | output [7:0] test_upstream_rx_8b_data, + | output [3:0] test_upstream_rx_state_machine, + | output test_upstream_tx_en, + | output [7:0] test_upstream_tx_8b_data, + | output [9:0] test_upstream_tx_10b_data |); | | lvds_bus_slave_top i_lvds_bus_slave( diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v index c647404..50c7f6e 100644 --- a/src/main/verilog/backBoardMstTop.v +++ b/src/main/verilog/backBoardMstTop.v @@ -23,10 +23,12 @@ module master_top( ); wire clk_400m; +wire clk_400m_a; wire clk_100m; +wire clk_100m_a; wire clk_50m; wire clk_50m_a; -wire clk_10m; +wire clk_10m_a; reg rst_n; @@ -35,39 +37,19 @@ wire lvds_up_din; reg rstn_d; -wire lock; - - - +wire reset_calib; +wire lock_o; +wire reset_stop; always@(posedge clk_10m) begin rstn_d <= resetn; rst_n <= rstn_d; end -//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module -oser_rst u_oser_rst( - .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed. - .rst_n(rst_n), - .pll_lock(lock), // trigged by PLL Lock - .reset_stop(reset_stop), // for DHCEN CE - .reset_calib(reset_calib), // for IDES and CLKDIV reset - .set_calib(), - .ready() -); - -DHCEN dhcen_inst ( - .CLKIN(clk_400m), - .CE(reset_stop), - .CLKOUT(clk_400m_a) -); - Gowin_PLLO Gowin_PLLO( - .lock(lock), + .lock(lock_o), .clkouta(clk_400m), - .clkoutc(clk_50m), - .clkoutd(clk_100m), .clkin(clock) ); @@ -85,15 +67,60 @@ TLVDS_IBUF lvds_upstream_in( ); -defparam Inst5_CLKDIVC.DIV_MODE = "5" ; -CLKDIV Inst5_CLKDIVC( - .RESETN (1'b1 ), - .HCLKIN (clk_50m), - .CALIB (1'b0 ), - .CLKOUT (clk_10m ) + +DHCEN dhcen_inst ( + .CLKIN(clk_400m), + .CE(reset_stop), + .CLKOUT(clk_400m_a) ); +//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module +oser_rst u_oser_rst( + .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed. + .rst_n(rst_n), + .pll_lock(lock_o), // trigged by PLL Lock + .reset_stop(reset_stop), // for DHCEN CE + .reset_calib(reset_calib), // for IDES and CLKDIV reset + .set_calib(), + .ready() +); + + +defparam Inst4_CLKDIVC.DIV_MODE="4"; +defparam Inst4_CLKDIVC.GSREN="false"; +CLKDIV Inst4_CLKDIVC( + .RESETN (~reset_calib), + .HCLKIN (clk_400m_a), + .CALIB (1'b0 ), + .CLKOUT (clk_100m_a) +); + + +defparam Inst2_CLKDIVC.DIV_MODE="2"; +defparam Inst2_CLKDIVC.GSREN="false"; +CLKDIV Inst2_CLKDIVC( + .RESETN (~reset_calib), + .HCLKIN (clk_100m_a), + .CALIB (1'b0 ), + .CLKOUT (clk_50m_a) +); + + +defparam Inst5_CLKDIVC.DIV_MODE="5"; +defparam Inst5_CLKDIVC.GSREN="false"; +CLKDIV Inst5_CLKDIVC( + .RESETN (~reset_calib), + .HCLKIN (clk_50m_a), + .CALIB (1'b0 ), + .CLKOUT (clk_10m_a) +); + + + + + + BackBoardMst i_BackBoardMst( .io_FSMC_addr(io_FSMC_addr), .io_FSMC_dataIn(io_FSMC_dataIn), @@ -103,12 +130,13 @@ BackBoardMst i_BackBoardMst( .io_FSMC_oen(io_FSMC_oen), .io_FSMC_wen(io_FSMC_wen), - .io_reset(~rst_n), - - .io_oser_pclk(clk_10m), - .io_oser_fclk(clk_50m), - .io_ides_pclk(clk_100m), - .io_ides_fclk(clk_400m), + .reset(~rst_n), + .clock(clk_10m_a), + .io_reset_calib(reset_calib), + .io_oser_pclk(clk_10m_a), + .io_oser_fclk(clk_50m_a), + .io_ides_pclk(clk_100m_a), + .io_ides_fclk(clk_400m_a), .io_lvds_down_dout(lvds_down_dout), .io_lvds_up_din(lvds_up_din) diff --git a/src/main/verilog/backBoardSlvTop.v b/src/main/verilog/backBoardSlvTop.v index 1060d9b..4ca052b 100644 --- a/src/main/verilog/backBoardSlvTop.v +++ b/src/main/verilog/backBoardSlvTop.v @@ -20,43 +20,35 @@ module slave_top( ); wire clk_400m; -wire clk_100m; -wire clk_50m; -wire clk_10m; +wire clk_400m_a; +wire clk_100m_a; +wire clk_50m_a; +wire clk_10m_a; +wire lock_o; +wire reset_stop; +wire reset_calib; -reg rst_n; -reg rstn_d; +reg rst_n; +reg rstn_d; wire [31:0] in; wire [31:0] out; wire [31:0] oe; -always@(posedge clk_10m) begin - rstn_d <= resetn; + +always@(posedge clk_10m_a) begin + rstn_d <= resetn; rst_n <= rstn_d; end - Gowin_PLLO Gowin_PLLO( - .lock(), - .clkouta(clk_400m), - .clkoutc(clk_50m), - .clkoutd(clk_100m), - .clkin(clock) - ); + .lock(lock_o), + .clkouta(clk_400m), + .clkin(clock) +); -generate - for( genvar i = 0; i < 32; i = i + 1 ) begin - IOBUF uut( - .O(in[i]), - .IO(digitalIO[i]), - .I(out[i]), - .OEN(~oe[i]) - ); - end -endgenerate TLVDS_OBUF lvds_downstream_out( @@ -87,31 +79,87 @@ TLVDS_IBUF lvds_upstream_in( ); -defparam Inst5_CLKDIVC.DIV_MODE = "5" ; -CLKDIV Inst5_CLKDIVC( - .RESETN (1'b1), - .HCLKIN (clk_50m), - .CALIB (1'b0), - .CLKOUT (clk_10m) +DHCEN dhcen_inst2 ( + .CLKIN(clk_400m), + .CE(reset_stop), + .CLKOUT(clk_400m_a) ); +//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module +oser_rst u_oser_rst( + .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed. + .rst_n(rst_n), + .pll_lock(lock_o), // trigged by PLL Lock + .reset_stop(reset_stop), // for DHCEN CE + .reset_calib(reset_calib), // for IDES and CLKDIV reset + .set_calib(), + .ready() +); + + +defparam Inst4_CLKDIVC.DIV_MODE="4"; +defparam Inst4_CLKDIVC.GSREN="false"; +CLKDIV Inst4_CLKDIVC( + .RESETN (~reset_calib), + .HCLKIN (clk_400m_a), + .CALIB (1'b0 ), + .CLKOUT (clk_100m_a) +); + + +defparam Inst2_CLKDIVC.DIV_MODE="2"; +defparam Inst2_CLKDIVC.GSREN="false"; +CLKDIV Inst2_CLKDIVC( + .RESETN (~reset_calib), + .HCLKIN (clk_100m_a), + .CALIB (1'b0 ), + .CLKOUT (clk_50m_a) +); + + +defparam Inst5_CLKDIVC.DIV_MODE="5"; +defparam Inst5_CLKDIVC.GSREN="false"; +CLKDIV Inst5_CLKDIVC( + .RESETN (~reset_calib), + .HCLKIN (clk_50m_a), + .CALIB (1'b0 ), + .CLKOUT (clk_10m_a) +); + + + + +generate + for( genvar i = 0; i < 32; i = i + 1 ) begin + IOBUF uut( + .O(in[i]), + .IO(digitalIO[i]), + .I(out[i]), + .OEN(~oe[i]) + ); + end +endgenerate + + + BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO( - .io_reset(~rst_n), + .reset(~rst_n), + .clock(clk_10m_a), + .io_reset_calib(reset_calib), + .io_oser_pclk(clk_10m_a), + .io_oser_fclk(clk_50m_a), + .io_ides_pclk(clk_100m_a), + .io_ides_fclk(clk_400m_a), - .io_oser_pclk(clk_10m), - .io_oser_fclk(clk_50m), - .io_ides_pclk(clk_100m), - .io_ides_fclk(clk_400m), + .io_lvds_down_din(lvds_down_din), + .io_lvds_down_dout(lvds_down_dout), + .io_lvds_up_din(lvds_up_din), + .io_lvds_up_dout(lvds_up_dout), - .io_lvds_down_din(lvds_down_din), - .io_lvds_down_dout(lvds_down_dout), - .io_lvds_up_din(lvds_up_din), - .io_lvds_up_dout(lvds_up_dout), - - .in(in), - .out(out), - .oe(oe) + .in(in), + .out(out), + .oe(oe) ); diff --git a/src/main/verilog/oser_rst.v b/src/main/verilog/oser_rst.v new file mode 100644 index 0000000..664b83a --- /dev/null +++ b/src/main/verilog/oser_rst.v @@ -0,0 +1,117 @@ +module oser_rst +(input clk_in, //!system clock or any other speed comparable with fabric, DO NOT use HCLK as fabric cannot work at so high speed. + input rst_n, //!from system reset + input pll_lock, //!RX PLL lock flag + output reg reset_stop, //!to DHCEN CE port + output reg reset_calib, //!to IDES/CLKDIV reset port + output reg set_calib, //!not used + output reg ready //!ready +); + +/******************************************************************************* + * OSER FSM States defined + *******************************************************************************/ + parameter STATE_IDLE = 5'b0000; + parameter STATE_SERDES_STOP_S = 5'b0001; + parameter STATE_SERDES_RST_S = 5'b0010; + parameter STATE_SERDES_RST_E = 5'b0011; + parameter STATE_SERDES_STOP_E = 5'b0100; + parameter STATE_SERDES_WAIT = 5'b0101; + parameter STATE_SERDES_CALIB = 5'b0110; + parameter STATE_SERDES_READY = 5'b0111; + /******************************************************************************* + //reg and wire definition + *******************************************************************************/ + reg [4:0] Fsm_serdes_rst_ctrl; + reg [9:0] Cnt_serdes_rst_ctrl; + + /*******************************************************************************/ + /*******************************************************************************/ + always @(posedge clk_in or negedge rst_n) + begin + if (~rst_n) begin + Fsm_serdes_rst_ctrl <= STATE_IDLE; + Cnt_serdes_rst_ctrl <= 'd0; + reset_stop <= 1'b0; + reset_calib <= 1'b0; + set_calib <= 1'b0; + ready <= 1'b0; + end + else begin + case(Fsm_serdes_rst_ctrl) + STATE_IDLE:begin//idle + if(pll_lock) + Fsm_serdes_rst_ctrl <= STATE_SERDES_STOP_S; + Cnt_serdes_rst_ctrl <= 'd0; + reset_stop <= 1'b0; + reset_calib <= 1'b0; + set_calib <= 1'b0; + ready <= 1'b0; + end + STATE_SERDES_STOP_S:begin + Cnt_serdes_rst_ctrl<=Cnt_serdes_rst_ctrl+1'b1; + if(Cnt_serdes_rst_ctrl[3])begin + // reset_stop <= 1'b1;// + reset_calib <= 1'b1;// + Fsm_serdes_rst_ctrl <= STATE_SERDES_RST_S; + end + else begin + reset_stop <= 1'b0; + end + end + STATE_SERDES_RST_S:begin + Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; + if(Cnt_serdes_rst_ctrl[5])begin + // reset_calib <= 1'b1; + reset_stop <= 1'b1; + Fsm_serdes_rst_ctrl <= STATE_SERDES_RST_E; + end + end + STATE_SERDES_RST_E:begin + Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; + if(Cnt_serdes_rst_ctrl[6])begin + reset_calib <= 1'b0; + Fsm_serdes_rst_ctrl <= STATE_SERDES_STOP_E; + end + end + STATE_SERDES_STOP_E:begin + Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; + if(Cnt_serdes_rst_ctrl[7])begin + reset_stop <= 1'b0; + Fsm_serdes_rst_ctrl <= STATE_SERDES_CALIB; + end + end + STATE_SERDES_CALIB:begin + Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; + if(Cnt_serdes_rst_ctrl[3:0] == 4'h04 )begin + set_calib <= 1'b1; + end + // if(Cnt_serdes_rst_ctrl[3:0] == 4'h08)begin + // set_calib <= 1'b0; + // end + if(Cnt_serdes_rst_ctrl[6])begin + set_calib <= 1'b0; + Fsm_serdes_rst_ctrl <= STATE_SERDES_READY; + end + end + + STATE_SERDES_READY:begin + Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1; + if(Cnt_serdes_rst_ctrl[8])begin + ready <= 1'b1; + // set_calib <= 1'b0; + Fsm_serdes_rst_ctrl <= STATE_SERDES_WAIT; + end + end + STATE_SERDES_WAIT:begin + if(~pll_lock)begin + Fsm_serdes_rst_ctrl<=STATE_IDLE; + end + end + default:begin + Fsm_serdes_rst_ctrl<=STATE_IDLE; + end + endcase + end + end +endmodule \ No newline at end of file