test pass

src/main/verilog/backBoardMstTop.v

@@ -23,10 +23,12 @@ module master_top(
 );
 
 wire clk_400m;
+wire clk_400m_a;
 wire clk_100m;
+wire clk_100m_a;
 wire clk_50m;
 wire clk_50m_a;
-wire clk_10m;
+wire clk_10m_a;
 
 reg        rst_n;
 
@@ -35,39 +37,19 @@ wire       lvds_up_din;
 
 reg        rstn_d;
 
-wire lock;
-
-
-
+wire       reset_calib;
+wire lock_o;
+wire       reset_stop;
 
 always@(posedge clk_10m) begin
   rstn_d <= resetn;
 	rst_n <= rstn_d;
 end
 
-//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
-oser_rst u_oser_rst(
-  .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
-  .rst_n(rst_n),
-  .pll_lock(lock), // trigged by PLL Lock
-  .reset_stop(reset_stop), // for DHCEN CE
-  .reset_calib(reset_calib), // for IDES and CLKDIV reset
-  .set_calib(), 
-  .ready()
-);
-
-DHCEN dhcen_inst (
-  .CLKIN(clk_400m),
-  .CE(reset_stop),
-  .CLKOUT(clk_400m_a)
-);
-
 
 Gowin_PLLO Gowin_PLLO(
-    .lock(lock),
+    .lock(lock_o),
     .clkouta(clk_400m),
-    .clkoutc(clk_50m),
-    .clkoutd(clk_100m),
     .clkin(clock)
 );
 
@@ -85,15 +67,60 @@ TLVDS_IBUF lvds_upstream_in(
 );
 
 
-defparam Inst5_CLKDIVC.DIV_MODE = "5" ;
-CLKDIV Inst5_CLKDIVC(
-  .RESETN (1'b1  ),
-  .HCLKIN (clk_50m),
-  .CALIB  (1'b0     ),
-  .CLKOUT (clk_10m  )
+
+DHCEN dhcen_inst (
+  .CLKIN(clk_400m),
+  .CE(reset_stop),
+  .CLKOUT(clk_400m_a)
 );
 
 
+//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
+oser_rst u_oser_rst(
+  .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
+  .rst_n(rst_n),
+  .pll_lock(lock_o), // trigged by PLL Lock
+  .reset_stop(reset_stop), // for DHCEN CE
+  .reset_calib(reset_calib), // for IDES and CLKDIV reset
+  .set_calib(), 
+  .ready()
+);
+
+
+defparam Inst4_CLKDIVC.DIV_MODE="4";
+defparam Inst4_CLKDIVC.GSREN="false";
+CLKDIV Inst4_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_400m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_100m_a)
+);
+
+
+defparam Inst2_CLKDIVC.DIV_MODE="2";
+defparam Inst2_CLKDIVC.GSREN="false";
+CLKDIV Inst2_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_100m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_50m_a)
+);
+
+
+defparam Inst5_CLKDIVC.DIV_MODE="5";
+defparam Inst5_CLKDIVC.GSREN="false";
+CLKDIV Inst5_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_50m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_10m_a)
+);
+
+
+
+
+
+
 BackBoardMst i_BackBoardMst(
     .io_FSMC_addr(io_FSMC_addr),
     .io_FSMC_dataIn(io_FSMC_dataIn),
@@ -103,12 +130,13 @@ BackBoardMst i_BackBoardMst(
     .io_FSMC_oen(io_FSMC_oen),
     .io_FSMC_wen(io_FSMC_wen),
 
-    .io_reset(~rst_n),
-
-    .io_oser_pclk(clk_10m), 
-    .io_oser_fclk(clk_50m),  
-    .io_ides_pclk(clk_100m),
-    .io_ides_fclk(clk_400m),
+    .reset(~rst_n),
+    .clock(clk_10m_a),
+    .io_reset_calib(reset_calib),
+    .io_oser_pclk(clk_10m_a),
+    .io_oser_fclk(clk_50m_a),
+    .io_ides_pclk(clk_100m_a),
+    .io_ides_fclk(clk_400m_a),
 
     .io_lvds_down_dout(lvds_down_dout),
     .io_lvds_up_din(lvds_up_din)