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test pass

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This commit is contained in:
RuigeLee
2023-09-14 19:16:17 +08:00
parent 6fd836fc9c
commit b098ca963e
6 changed files with 466 additions and 255 deletions
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102
src/main/verilog/backBoardMstTop.v
View File

@@ -23,10 +23,12 @@ module master_top(
);
wire clk_400m;
wire clk_400m_a;
wire clk_100m;
wire clk_100m_a;
wire clk_50m;
wire clk_50m_a;
wire clk_10m;
wire clk_10m_a;
reg rst_n;
@@ -35,39 +37,19 @@ wire lvds_up_din;
reg rstn_d;
wire lock;
wire reset_calib;
wire lock_o;
wire reset_stop;
always@(posedge clk_10m) begin
rstn_d <= resetn;
rst_n <= rstn_d;
end
//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
oser_rst u_oser_rst(
.clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
.rst_n(rst_n),
.pll_lock(lock), // trigged by PLL Lock
.reset_stop(reset_stop), // for DHCEN CE
.reset_calib(reset_calib), // for IDES and CLKDIV reset
.set_calib(),
.ready()
);
DHCEN dhcen_inst (
.CLKIN(clk_400m),
.CE(reset_stop),
.CLKOUT(clk_400m_a)
);
Gowin_PLLO Gowin_PLLO(
.lock(lock),
.lock(lock_o),
.clkouta(clk_400m),
.clkoutc(clk_50m),
.clkoutd(clk_100m),
.clkin(clock)
);
@@ -85,15 +67,60 @@ TLVDS_IBUF lvds_upstream_in(
);
defparam Inst5_CLKDIVC.DIV_MODE = "5" ;
CLKDIV Inst5_CLKDIVC(
.RESETN (1'b1 ),
.HCLKIN (clk_50m),
.CALIB (1'b0 ),
.CLKOUT (clk_10m )
DHCEN dhcen_inst (
.CLKIN(clk_400m),
.CE(reset_stop),
.CLKOUT(clk_400m_a)
);
//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
oser_rst u_oser_rst(
.clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
.rst_n(rst_n),
.pll_lock(lock_o), // trigged by PLL Lock
.reset_stop(reset_stop), // for DHCEN CE
.reset_calib(reset_calib), // for IDES and CLKDIV reset
.set_calib(),
.ready()
);
defparam Inst4_CLKDIVC.DIV_MODE="4";
defparam Inst4_CLKDIVC.GSREN="false";
CLKDIV Inst4_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_400m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_100m_a)
);
defparam Inst2_CLKDIVC.DIV_MODE="2";
defparam Inst2_CLKDIVC.GSREN="false";
CLKDIV Inst2_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_100m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_50m_a)
);
defparam Inst5_CLKDIVC.DIV_MODE="5";
defparam Inst5_CLKDIVC.GSREN="false";
CLKDIV Inst5_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_50m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_10m_a)
);
BackBoardMst i_BackBoardMst(
.io_FSMC_addr(io_FSMC_addr),
.io_FSMC_dataIn(io_FSMC_dataIn),
@@ -103,12 +130,13 @@ BackBoardMst i_BackBoardMst(
.io_FSMC_oen(io_FSMC_oen),
.io_FSMC_wen(io_FSMC_wen),
.io_reset(~rst_n),
.io_oser_pclk(clk_10m),
.io_oser_fclk(clk_50m),
.io_ides_pclk(clk_100m),
.io_ides_fclk(clk_400m),
.reset(~rst_n),
.clock(clk_10m_a),
.io_reset_calib(reset_calib),
.io_oser_pclk(clk_10m_a),
.io_oser_fclk(clk_50m_a),
.io_ides_pclk(clk_100m_a),
.io_ides_fclk(clk_400m_a),
.io_lvds_down_dout(lvds_down_dout),
.io_lvds_up_din(lvds_up_din)

134
src/main/verilog/backBoardSlvTop.v
View File

@@ -20,43 +20,35 @@ module slave_top(
);
wire clk_400m;
wire clk_100m;
wire clk_50m;
wire clk_10m;
wire clk_400m_a;
wire clk_100m_a;
wire clk_50m_a;
wire clk_10m_a;
wire lock_o;
wire reset_stop;
wire reset_calib;
reg rst_n;
reg rstn_d;
reg rst_n;
reg rstn_d;
wire [31:0] in;
wire [31:0] out;
wire [31:0] oe;
always@(posedge clk_10m) begin
rstn_d <= resetn;
always@(posedge clk_10m_a) begin
rstn_d <= resetn;
rst_n <= rstn_d;
end
Gowin_PLLO Gowin_PLLO(
.lock(),
.clkouta(clk_400m),
.clkoutc(clk_50m),
.clkoutd(clk_100m),
.clkin(clock)
);
.lock(lock_o),
.clkouta(clk_400m),
.clkin(clock)
);
generate
for( genvar i = 0; i < 32; i = i + 1 ) begin
IOBUF uut(
.O(in[i]),
.IO(digitalIO[i]),
.I(out[i]),
.OEN(~oe[i])
);
end
endgenerate
TLVDS_OBUF lvds_downstream_out(
@@ -87,31 +79,87 @@ TLVDS_IBUF lvds_upstream_in(
);
defparam Inst5_CLKDIVC.DIV_MODE = "5" ;
CLKDIV Inst5_CLKDIVC(
.RESETN (1'b1),
.HCLKIN (clk_50m),
.CALIB (1'b0),
.CLKOUT (clk_10m)
DHCEN dhcen_inst2 (
.CLKIN(clk_400m),
.CE(reset_stop),
.CLKOUT(clk_400m_a)
);
//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
oser_rst u_oser_rst(
.clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
.rst_n(rst_n),
.pll_lock(lock_o), // trigged by PLL Lock
.reset_stop(reset_stop), // for DHCEN CE
.reset_calib(reset_calib), // for IDES and CLKDIV reset
.set_calib(),
.ready()
);
defparam Inst4_CLKDIVC.DIV_MODE="4";
defparam Inst4_CLKDIVC.GSREN="false";
CLKDIV Inst4_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_400m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_100m_a)
);
defparam Inst2_CLKDIVC.DIV_MODE="2";
defparam Inst2_CLKDIVC.GSREN="false";
CLKDIV Inst2_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_100m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_50m_a)
);
defparam Inst5_CLKDIVC.DIV_MODE="5";
defparam Inst5_CLKDIVC.GSREN="false";
CLKDIV Inst5_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_50m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_10m_a)
);
generate
for( genvar i = 0; i < 32; i = i + 1 ) begin
IOBUF uut(
.O(in[i]),
.IO(digitalIO[i]),
.I(out[i]),
.OEN(~oe[i])
);
end
endgenerate
BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO(
.io_reset(~rst_n),
.reset(~rst_n),
.clock(clk_10m_a),
.io_reset_calib(reset_calib),
.io_oser_pclk(clk_10m_a),
.io_oser_fclk(clk_50m_a),
.io_ides_pclk(clk_100m_a),
.io_ides_fclk(clk_400m_a),
.io_oser_pclk(clk_10m),
.io_oser_fclk(clk_50m),
.io_ides_pclk(clk_100m),
.io_ides_fclk(clk_400m),
.io_lvds_down_din(lvds_down_din),
.io_lvds_down_dout(lvds_down_dout),
.io_lvds_up_din(lvds_up_din),
.io_lvds_up_dout(lvds_up_dout),
.io_lvds_down_din(lvds_down_din),
.io_lvds_down_dout(lvds_down_dout),
.io_lvds_up_din(lvds_up_din),
.io_lvds_up_dout(lvds_up_dout),
.in(in),
.out(out),
.oe(oe)
.in(in),
.out(out),
.oe(oe)
);

117
src/main/verilog/oser_rst.v Normal file
View File

@@ -0,0 +1,117 @@
module oser_rst
(input clk_in, //!system clock or any other speed comparable with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
input rst_n, //!from system reset
input pll_lock, //!RX PLL lock flag
output reg reset_stop, //!to DHCEN CE port
output reg reset_calib, //!to IDES/CLKDIV reset port
output reg set_calib, //!not used
output reg ready //!ready
);
/*******************************************************************************
* OSER FSM States defined
*******************************************************************************/
parameter STATE_IDLE = 5'b0000;
parameter STATE_SERDES_STOP_S = 5'b0001;
parameter STATE_SERDES_RST_S = 5'b0010;
parameter STATE_SERDES_RST_E = 5'b0011;
parameter STATE_SERDES_STOP_E = 5'b0100;
parameter STATE_SERDES_WAIT = 5'b0101;
parameter STATE_SERDES_CALIB = 5'b0110;
parameter STATE_SERDES_READY = 5'b0111;
/*******************************************************************************
//reg and wire definition
*******************************************************************************/
reg [4:0] Fsm_serdes_rst_ctrl;
reg [9:0] Cnt_serdes_rst_ctrl;
/*******************************************************************************/
/*******************************************************************************/
always @(posedge clk_in or negedge rst_n)
begin
if (~rst_n) begin
Fsm_serdes_rst_ctrl <= STATE_IDLE;
Cnt_serdes_rst_ctrl <= 'd0;
reset_stop <= 1'b0;
reset_calib <= 1'b0;
set_calib <= 1'b0;
ready <= 1'b0;
end
else begin
case(Fsm_serdes_rst_ctrl)
STATE_IDLE:begin//idle
if(pll_lock)
Fsm_serdes_rst_ctrl <= STATE_SERDES_STOP_S;
Cnt_serdes_rst_ctrl <= 'd0;
reset_stop <= 1'b0;
reset_calib <= 1'b0;
set_calib <= 1'b0;
ready <= 1'b0;
end
STATE_SERDES_STOP_S:begin
Cnt_serdes_rst_ctrl<=Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[3])begin
// reset_stop <= 1'b1;//
reset_calib <= 1'b1;//
Fsm_serdes_rst_ctrl <= STATE_SERDES_RST_S;
end
else begin
reset_stop <= 1'b0;
end
end
STATE_SERDES_RST_S:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[5])begin
// reset_calib <= 1'b1;
reset_stop <= 1'b1;
Fsm_serdes_rst_ctrl <= STATE_SERDES_RST_E;
end
end
STATE_SERDES_RST_E:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[6])begin
reset_calib <= 1'b0;
Fsm_serdes_rst_ctrl <= STATE_SERDES_STOP_E;
end
end
STATE_SERDES_STOP_E:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[7])begin
reset_stop <= 1'b0;
Fsm_serdes_rst_ctrl <= STATE_SERDES_CALIB;
end
end
STATE_SERDES_CALIB:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[3:0] == 4'h04 )begin
set_calib <= 1'b1;
end
// if(Cnt_serdes_rst_ctrl[3:0] == 4'h08)begin
// set_calib <= 1'b0;
// end
if(Cnt_serdes_rst_ctrl[6])begin
set_calib <= 1'b0;
Fsm_serdes_rst_ctrl <= STATE_SERDES_READY;
end
end
STATE_SERDES_READY:begin
Cnt_serdes_rst_ctrl <= Cnt_serdes_rst_ctrl+1'b1;
if(Cnt_serdes_rst_ctrl[8])begin
ready <= 1'b1;
// set_calib <= 1'b0;
Fsm_serdes_rst_ctrl <= STATE_SERDES_WAIT;
end
end
STATE_SERDES_WAIT:begin
if(~pll_lock)begin
Fsm_serdes_rst_ctrl<=STATE_IDLE;
end
end
default:begin
Fsm_serdes_rst_ctrl<=STATE_IDLE;
end
endcase
end
end
endmodule