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test pass

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This commit is contained in:
RuigeLee
2023-09-14 19:16:17 +08:00
parent 6fd836fc9c
commit b098ca963e
6 changed files with 466 additions and 255 deletions
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8
src/main/scala/backBoard/BackBoardSlv.scala
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@@ -59,7 +59,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
}
when( lvdsSlv.io.downstream_rx_crc_valid ){
when( ~downstream_rx_crc_err ){
when( ~lvdsSlv.io.downstream_rx_crc_err ){
downReg := downRegTemp
}
}
@@ -86,7 +86,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
trait BackBoardSlvUp{ this: BackBoardSlvBase =>
val upCnt = RegInit(31.U(6.W))
val upCnt = RegInit(15.U(6.W))
val upTimeoutEn = RegInit( false.B )
val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
val ( _, upTimeout ) = Counter( Range( 0,1000 ), upTimeoutEn, upTimeoutRst )
@@ -98,7 +98,7 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
when( upTimeout ){
upTimeoutEn := false.B
} .elsewhen( upCnt === 31.U ){
} .elsewhen( upCnt === 15.U ){
upTimeoutEn := false.B
} .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
upTimeoutEn := true.B
@@ -107,7 +107,7 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
when( upTimeout ){
upCnt := 0.U
}.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
when(upCnt === 31.U){
when(upCnt === 15.U){
upCnt := 0.U
} .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
upCnt := upCnt + 1.U