代码清理
This commit is contained in:
RuigeLee
@@ -683,7 +683,6 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
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val wishbone = Module(new MacTileLink(slv_edge, mst_edge))
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wishbone.io.asyncReset := io.asyncReset
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wishbone.io.tlSlv.A.valid := slv_bus.a.valid
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wishbone.io.tlSlv.A.bits := slv_bus.a.bits
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@@ -723,12 +722,9 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
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wishbone.io.DeferLatched := DeferLatched
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wishbone.io.CarrierSenseLost := CarrierSenseLost
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wishbone.io.MTxClk := io.mtx_clk_pad_i
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PerPacketCrcEn := wishbone.io.PerPacketCrcEn
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PerPacketPad := wishbone.io.PerPacketPad
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wishbone.io.MRxClk := io.mrx_clk_pad_i
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wishbone.io.r_TxEn := r_TxEn
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wishbone.io.r_RxEn := r_RxEn
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wishbone.io.r_TxBDNum := r_TxBDNum
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@@ -815,40 +811,40 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
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val macTileLinkTX = withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTX))
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val macTileLinkTx = withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
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// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
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val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTX.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
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val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
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wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync
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withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ){
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macTileLinkTX.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
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macTileLinkTX.io.TxStartFrm_sync := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
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macTileLinkTX.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)
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macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
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macTileLinkTx.io.TxStartFrm_sync := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
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macTileLinkTx.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)
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}
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wishbone.io.TxStartFrm_syncb := ShiftRegister( macTileLinkTX.io.TxStartFrm_sync, 2, false.B, true.B )
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wishbone.io.TxStartFrm_syncb := ShiftRegister( macTileLinkTx.io.TxStartFrm_sync, 2, false.B, true.B )
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RstDeferLatched := macTileLinkTX.io.RstDeferLatched
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TxStartFrm := macTileLinkTX.io.TxStartFrm
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TxEndFrm := macTileLinkTX.io.TxEndFrm
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TxData := macTileLinkTX.io.TxData
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RstDeferLatched := macTileLinkTx.io.RstDeferLatched
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TxStartFrm := macTileLinkTx.io.TxStartFrm
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TxEndFrm := macTileLinkTx.io.TxEndFrm
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TxData := macTileLinkTx.io.TxData
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wishbone.io.TxUnderRun := TxUnderRun
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TxUnderRun := macTileLinkTX.io.TxUnderRun
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macTileLinkTX.io.TxUnderRun_wb := wishbone.io.TxUnderRun_wb
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TxUnderRun := macTileLinkTx.io.TxUnderRun
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macTileLinkTx.io.TxUnderRun_wb := wishbone.io.TxUnderRun_wb
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macTileLinkTX.io.TxData_wb := wishbone.io.TxData_wb
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macTileLinkTX.io.TxValidBytesLatched := wishbone.io.TxValidBytesLatched
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macTileLinkTX.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
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macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb
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macTileLinkTx.io.TxValidBytesLatched := wishbone.io.TxValidBytesLatched
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macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
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wishbone.io.TxUsedData := TxUsedData
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macTileLinkTX.io.TxUsedData := TxUsedData
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macTileLinkTx.io.TxUsedData := TxUsedData
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macTileLinkTX.io.TxRetry := TxRetry
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macTileLinkTX.io.TxAbort := TxAbort
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macTileLinkTX.io.TxDone := TxDone
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macTileLinkTx.io.TxRetry := TxRetry
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macTileLinkTx.io.TxAbort := TxAbort
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macTileLinkTx.io.TxDone := TxDone
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wishbone.io.TxRetrySync := ShiftRegister( TxRetry, 2, false.B, true.B )
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wishbone.io.TxAbortSync := ShiftRegister( TxAbort, 2, false.B, true.B )
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@@ -875,61 +871,61 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
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val macTileLinkRX = withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRX) )
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val macTileLinkRx = withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
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wishbone.io.RxDataLatched2_rxclk := macTileLinkRX.io.RxDataLatched2
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wishbone.io.RxDataLatched2_rxclk := macTileLinkRx.io.RxDataLatched2
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val WriteRxDataToFifoSync = ShiftRegister(macTileLinkRX.io.WriteRxDataToFifo, 2, false.B, true.B)
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val WriteRxDataToFifoSync = ShiftRegister(macTileLinkRx.io.WriteRxDataToFifo, 2, false.B, true.B)
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wishbone.io.WriteRxDataToFifoSync := WriteRxDataToFifoSync
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val RxAbortSync = ShiftRegister( macTileLinkRX.io.RxAbortLatched, 2, false.B, true.B )
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val RxAbortSync = ShiftRegister( macTileLinkRx.io.RxAbortLatched, 2, false.B, true.B )
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wishbone.io.RxAbortSync := RxAbortSync
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val ShiftEndedSync = ShiftRegister( macTileLinkRX.io.ShiftEnded_rck, 2, false.B, true.B )
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val ShiftEndedSync = ShiftRegister( macTileLinkRx.io.ShiftEnded_rck, 2, false.B, true.B )
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wishbone.io.ShiftEndedSync := ShiftEndedSync
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val SyncRxStartFrmSync = ShiftRegister(macTileLinkRX.io.LatchedRxStartFrm, 2, false.B, true.B)
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val SyncRxStartFrmSync = ShiftRegister(macTileLinkRx.io.LatchedRxStartFrm, 2, false.B, true.B)
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wishbone.io.SyncRxStartFrmSync := SyncRxStartFrmSync
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wishbone.io.RxStatusWriteLatchedSyncb = ShiftRegister(RxStatusWriteLatchedSync, 2, false.B, true.B)
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wishbone.io.RxStatusWriteLatchedSyncb := ShiftRegister(RxStatusWriteLatchedSync, 2, false.B, true.B)
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wishbone.io.LatchedRxLength_rxclk := macTileLinkRX.io.LatchedRxLength
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wishbone.io.RxStatusInLatched_rxclk := macTileLinkRX.io.RxStatusInLatched
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wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength
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wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched
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// Busy Interrupt
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val Busy_IRQ_sync = ShiftRegister(macTileLinkRX.io.Busy_IRQ_rck, 2)
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val Busy_IRQ_sync = ShiftRegister(macTileLinkRx.io.Busy_IRQ_rck, 2)
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wishbone.io.Busy_IRQ_sync := Busy_IRQ_sync
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withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) {
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RxStatusWriteLatchedSync := ShiftRegister(wishbone.io.RxStatusWriteLatched, 2, false.B, true.B)
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macTileLinkRX.io.ShiftEndedSyncb := ShiftRegister( ShiftEndedSync, 2, false.B, true.B)
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macTileLinkRX.io.RxAbortSyncb := ShiftRegister( RxAbortSync, 2, false.B, true.B )
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macTileLinkRX.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B )
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macTileLinkRx.io.ShiftEndedSyncb := ShiftRegister( ShiftEndedSync, 2, false.B, true.B)
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macTileLinkRx.io.RxAbortSyncb := ShiftRegister( RxAbortSync, 2, false.B, true.B )
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macTileLinkRx.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B )
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macTileLinkRX.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync, 2, false.B, true.B )
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macTileLinkRX.io.SyncRxStartFrmSyncb := ShiftRegister( SyncRxStartFrmSync, 2, false.B, true.B )
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macTileLinkRX.io.RxReady := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B )
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macTileLinkRx.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync, 2, false.B, true.B )
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macTileLinkRx.io.SyncRxStartFrmSyncb := ShiftRegister( SyncRxStartFrmSync, 2, false.B, true.B )
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macTileLinkRx.io.RxReady := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B )
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}
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macTileLinkRX.io.RxData := RxData
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macTileLinkRX.io.RxAbort := RxAbort_latch_wire
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macTileLinkRX.io.RxValid := RxValid
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macTileLinkRx.io.RxData := RxData
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macTileLinkRx.io.RxAbort := RxAbort_latch_wire
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macTileLinkRx.io.RxValid := RxValid
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macTileLinkRX.io.RxStartFrm := RxStartFrm
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macTileLinkRX.io.RxEndFrm := RxEndFrm
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macTileLinkRx.io.RxStartFrm := RxStartFrm
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macTileLinkRx.io.RxEndFrm := RxEndFrm
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macTileLinkRX.io.RxLength := RxByteCnt
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macTileLinkRX.io.LoadRxStatus := LoadRxStatus
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macTileLinkRX.io.RxStatusIn := wishbone.io.RxStatusIn
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macTileLinkRx.io.RxLength := RxByteCnt
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macTileLinkRx.io.LoadRxStatus := LoadRxStatus
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macTileLinkRx.io.RxStatusIn := wishbone.io.RxStatusIn
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