diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala index 0477620..63d5489 100644 --- a/src/main/scala/mac/MAC.scala +++ b/src/main/scala/mac/MAC.scala @@ -683,7 +683,6 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul val wishbone = Module(new MacTileLink(slv_edge, mst_edge)) - wishbone.io.asyncReset := io.asyncReset wishbone.io.tlSlv.A.valid := slv_bus.a.valid wishbone.io.tlSlv.A.bits := slv_bus.a.bits @@ -723,12 +722,9 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul wishbone.io.DeferLatched := DeferLatched wishbone.io.CarrierSenseLost := CarrierSenseLost - wishbone.io.MTxClk := io.mtx_clk_pad_i PerPacketCrcEn := wishbone.io.PerPacketCrcEn PerPacketPad := wishbone.io.PerPacketPad - wishbone.io.MRxClk := io.mrx_clk_pad_i - wishbone.io.r_TxEn := r_TxEn wishbone.io.r_RxEn := r_RxEn wishbone.io.r_TxBDNum := r_TxBDNum @@ -815,40 +811,40 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul - val macTileLinkTX = withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTX)) + val macTileLinkTx = withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx)) // Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I - val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTX.io.ReadTxDataFromFifo_tck, 2, false.B, true.B) + val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B) wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ){ - macTileLinkTX.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B) - macTileLinkTX.io.TxStartFrm_sync := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk - macTileLinkTX.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B) + macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B) + macTileLinkTx.io.TxStartFrm_sync := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk + macTileLinkTx.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B) } - wishbone.io.TxStartFrm_syncb := ShiftRegister( macTileLinkTX.io.TxStartFrm_sync, 2, false.B, true.B ) + wishbone.io.TxStartFrm_syncb := ShiftRegister( macTileLinkTx.io.TxStartFrm_sync, 2, false.B, true.B ) - RstDeferLatched := macTileLinkTX.io.RstDeferLatched - TxStartFrm := macTileLinkTX.io.TxStartFrm - TxEndFrm := macTileLinkTX.io.TxEndFrm - TxData := macTileLinkTX.io.TxData + RstDeferLatched := macTileLinkTx.io.RstDeferLatched + TxStartFrm := macTileLinkTx.io.TxStartFrm + TxEndFrm := macTileLinkTx.io.TxEndFrm + TxData := macTileLinkTx.io.TxData wishbone.io.TxUnderRun := TxUnderRun - TxUnderRun := macTileLinkTX.io.TxUnderRun - macTileLinkTX.io.TxUnderRun_wb := wishbone.io.TxUnderRun_wb + TxUnderRun := macTileLinkTx.io.TxUnderRun + macTileLinkTx.io.TxUnderRun_wb := wishbone.io.TxUnderRun_wb - macTileLinkTX.io.TxData_wb := wishbone.io.TxData_wb - macTileLinkTX.io.TxValidBytesLatched := wishbone.io.TxValidBytesLatched - macTileLinkTX.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb + macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb + macTileLinkTx.io.TxValidBytesLatched := wishbone.io.TxValidBytesLatched + macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb wishbone.io.TxUsedData := TxUsedData - macTileLinkTX.io.TxUsedData := TxUsedData + macTileLinkTx.io.TxUsedData := TxUsedData - macTileLinkTX.io.TxRetry := TxRetry - macTileLinkTX.io.TxAbort := TxAbort - macTileLinkTX.io.TxDone := TxDone + macTileLinkTx.io.TxRetry := TxRetry + macTileLinkTx.io.TxAbort := TxAbort + macTileLinkTx.io.TxDone := TxDone wishbone.io.TxRetrySync := ShiftRegister( TxRetry, 2, false.B, true.B ) wishbone.io.TxAbortSync := ShiftRegister( TxAbort, 2, false.B, true.B ) @@ -875,61 +871,61 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul - val macTileLinkRX = withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRX) ) + val macTileLinkRx = withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) ) - wishbone.io.RxDataLatched2_rxclk := macTileLinkRX.io.RxDataLatched2 + wishbone.io.RxDataLatched2_rxclk := macTileLinkRx.io.RxDataLatched2 - val WriteRxDataToFifoSync = ShiftRegister(macTileLinkRX.io.WriteRxDataToFifo, 2, false.B, true.B) + val WriteRxDataToFifoSync = ShiftRegister(macTileLinkRx.io.WriteRxDataToFifo, 2, false.B, true.B) wishbone.io.WriteRxDataToFifoSync := WriteRxDataToFifoSync - val RxAbortSync = ShiftRegister( macTileLinkRX.io.RxAbortLatched, 2, false.B, true.B ) + val RxAbortSync = ShiftRegister( macTileLinkRx.io.RxAbortLatched, 2, false.B, true.B ) wishbone.io.RxAbortSync := RxAbortSync - val ShiftEndedSync = ShiftRegister( macTileLinkRX.io.ShiftEnded_rck, 2, false.B, true.B ) + val ShiftEndedSync = ShiftRegister( macTileLinkRx.io.ShiftEnded_rck, 2, false.B, true.B ) wishbone.io.ShiftEndedSync := ShiftEndedSync - val SyncRxStartFrmSync = ShiftRegister(macTileLinkRX.io.LatchedRxStartFrm, 2, false.B, true.B) + val SyncRxStartFrmSync = ShiftRegister(macTileLinkRx.io.LatchedRxStartFrm, 2, false.B, true.B) wishbone.io.SyncRxStartFrmSync := SyncRxStartFrmSync - wishbone.io.RxStatusWriteLatchedSyncb = ShiftRegister(RxStatusWriteLatchedSync, 2, false.B, true.B) + wishbone.io.RxStatusWriteLatchedSyncb := ShiftRegister(RxStatusWriteLatchedSync, 2, false.B, true.B) - wishbone.io.LatchedRxLength_rxclk := macTileLinkRX.io.LatchedRxLength - wishbone.io.RxStatusInLatched_rxclk := macTileLinkRX.io.RxStatusInLatched + wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength + wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched // Busy Interrupt - val Busy_IRQ_sync = ShiftRegister(macTileLinkRX.io.Busy_IRQ_rck, 2) + val Busy_IRQ_sync = ShiftRegister(macTileLinkRx.io.Busy_IRQ_rck, 2) wishbone.io.Busy_IRQ_sync := Busy_IRQ_sync withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) { RxStatusWriteLatchedSync := ShiftRegister(wishbone.io.RxStatusWriteLatched, 2, false.B, true.B) - macTileLinkRX.io.ShiftEndedSyncb := ShiftRegister( ShiftEndedSync, 2, false.B, true.B) - macTileLinkRX.io.RxAbortSyncb := ShiftRegister( RxAbortSync, 2, false.B, true.B ) - macTileLinkRX.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B ) + macTileLinkRx.io.ShiftEndedSyncb := ShiftRegister( ShiftEndedSync, 2, false.B, true.B) + macTileLinkRx.io.RxAbortSyncb := ShiftRegister( RxAbortSync, 2, false.B, true.B ) + macTileLinkRx.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B ) - macTileLinkRX.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync, 2, false.B, true.B ) - macTileLinkRX.io.SyncRxStartFrmSyncb := ShiftRegister( SyncRxStartFrmSync, 2, false.B, true.B ) - macTileLinkRX.io.RxReady := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B ) + macTileLinkRx.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync, 2, false.B, true.B ) + macTileLinkRx.io.SyncRxStartFrmSyncb := ShiftRegister( SyncRxStartFrmSync, 2, false.B, true.B ) + macTileLinkRx.io.RxReady := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B ) } - macTileLinkRX.io.RxData := RxData - macTileLinkRX.io.RxAbort := RxAbort_latch_wire - macTileLinkRX.io.RxValid := RxValid + macTileLinkRx.io.RxData := RxData + macTileLinkRx.io.RxAbort := RxAbort_latch_wire + macTileLinkRx.io.RxValid := RxValid - macTileLinkRX.io.RxStartFrm := RxStartFrm - macTileLinkRX.io.RxEndFrm := RxEndFrm + macTileLinkRx.io.RxStartFrm := RxStartFrm + macTileLinkRx.io.RxEndFrm := RxEndFrm - macTileLinkRX.io.RxLength := RxByteCnt - macTileLinkRX.io.LoadRxStatus := LoadRxStatus - macTileLinkRX.io.RxStatusIn := wishbone.io.RxStatusIn + macTileLinkRx.io.RxLength := RxByteCnt + macTileLinkRx.io.LoadRxStatus := LoadRxStatus + macTileLinkRx.io.RxStatusIn := wishbone.io.RxStatusIn diff --git a/src/main/scala/mac/MacTileLinkRx.scala b/src/main/scala/mac/MacTileLinkRx.scala new file mode 100644 index 0000000..d77b826 --- /dev/null +++ b/src/main/scala/mac/MacTileLinkRx.scala @@ -0,0 +1,168 @@ +package MAC + +import chisel3._ +import chisel3.util._ + + + +class MacTileLinkRxIO extends Bundle{ + val RxDataLatched2 = Output(UInt(32.W)) + val WriteRxDataToFifo = Output(Bool()) + val RxAbortLatched = Output(Bool()) + val LatchedRxLength = Output(UInt(16.W)) + val RxStatusInLatched = Output( UInt(9.W) ) + val ShiftEnded_rck = Output(Bool()) + val LatchedRxStartFrm = Output(Bool()) + + val RxLength = Input(UInt(16.W)) + val LoadRxStatus = Input(Bool()) + val RxStatusIn = Input(UInt(9.W)) + val ShiftEndedSyncb = Input(Bool()) + val RxAbortSyncb = Input(Bool()) + val WriteRxDataToFifoSyncb = Input(Bool()) + val SyncRxStartFrmSyncb = Input(Bool()) + + val Busy_IRQ_rck = Output(Bool()) + val Busy_IRQ_syncb = Input(Bool()) + + val RxData = Input(UInt(8.W)) // Received data byte (from PHY) + val RxAbort = Input(Bool()) + val RxValid = Input(Bool()) + val RxReady = Input(Bool()) + val RxStartFrm = Input(Bool()) + val RxEndFrm = Input(Bool()) +} + + +class MacTileLinkRx extends Module with RequireAsyncReset{ + val io = IO(new MacTileLinkRxIO) + + val RxDataLatched2 = RegInit(0.U(32.W)); io.RxDataLatched2 := RxDataLatched2 + val RxDataLatched1 = RegInit(0.U(24.W)) // Little Endian Byte Ordering[23:0] + val RxValidBytes = RegInit(1.U(2.W)) + val RxByteCnt = RegInit(0.U(2.W)) + val LastByteIn = RegInit(false.B) + val ShiftWillEnd = RegInit(false.B) + val WriteRxDataToFifo = RegInit(false.B); io.WriteRxDataToFifo := WriteRxDataToFifo + val RxAbortLatched = RegInit(false.B); io.RxAbortLatched := RxAbortLatched + + val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength + val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched + + val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck + val RxEnableWindow = RegInit(false.B) + + val LatchedRxStartFrm = RegInit(false.B); io.LatchedRxStartFrm := LatchedRxStartFrm + + val Busy_IRQ_rck = RegInit(false.B); io.Busy_IRQ_rck := Busy_IRQ_rck + + + + + // Indicating that last byte is being reveived + when(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){ + LastByteIn := false.B + } .elsewhen(io.RxValid & io.RxReady & io.RxEndFrm & ~(RxByteCnt.andR) & RxEnableWindow){ + LastByteIn := true.B + } + + // Indicating that data reception will end + val StartShiftWillEnd = LastByteIn | io.RxValid & io.RxEndFrm & RxByteCnt.andR & RxEnableWindow + when(ShiftEnded_rck | io.RxAbort){ + ShiftWillEnd := false.B + } .elsewhen(StartShiftWillEnd){ + ShiftWillEnd := true.B + } + + // Receive byte counter + when(ShiftEnded_rck | io.RxAbort){ + RxByteCnt := 0.U + } .elsewhen(io.RxValid & io.RxStartFrm & io.RxReady){ + RxByteCnt := 1.U + } .elsewhen(io.RxValid & RxEnableWindow & io.RxReady | LastByteIn){ + RxByteCnt := RxByteCnt + 1.U + } + + // Indicates how many bytes are valid within the last word + when(io.RxValid & io.RxStartFrm){ + RxValidBytes := 1.U + } .elsewhen(io.RxValid & ~LastByteIn & ~io.RxStartFrm & RxEnableWindow){ + RxValidBytes := RxValidBytes + 1.U + } + + when(io.RxValid & io.RxReady & ~LastByteIn){ + when(io.RxStartFrm){ + RxDataLatched1 := Cat(RxDataLatched1(23, 8), io.RxData)// Little Endian Byte Ordering + } .elsewhen(RxEnableWindow){ + RxDataLatched1 := Mux1H(Seq( + ( RxByteCnt === 0.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),// Little Endian Byte Ordering + ( RxByteCnt === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)), + ( RxByteCnt === 2.U ) -> Cat( io.RxData, RxDataLatched1(15,0)), + ( RxByteCnt === 3.U ) -> RxDataLatched1, + )) + } + } + + // Indicating start of the reception process + val SetWriteRxDataToFifo = + (io.RxValid & io.RxReady & ~io.RxStartFrm & RxEnableWindow & (RxByteCnt.andR)) | + (ShiftWillEnd & LastByteIn & (RxByteCnt.andR)) + + // Assembling data that will be written to the rx_fifo + when(SetWriteRxDataToFifo & ~ShiftWillEnd){ + RxDataLatched2 := Cat(io.RxData, RxDataLatched1)// Little Endian Byte Ordering + } .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){ + RxDataLatched2 := Mux1H(Seq( // Little Endian Byte Ordering + ( RxValidBytes === 0.U ) -> Cat(io.RxData, RxDataLatched1), + ( RxValidBytes === 1.U ) -> Cat(0.U(24.W), RxDataLatched1(7,0) ), + ( RxValidBytes === 2.U ) -> Cat(0.U(16.W), RxDataLatched1(15, 0) ), + ( RxValidBytes === 3.U ) -> Cat(0.U(8.W), RxDataLatched1 ), + )) + } + + when(SetWriteRxDataToFifo & ~io.RxAbort){ + WriteRxDataToFifo := true.B + } .elsewhen(io.WriteRxDataToFifoSyncb | io.RxAbort){ + WriteRxDataToFifo := false.B + } + + + when(io.RxStartFrm & ~io.SyncRxStartFrmSyncb){ + LatchedRxStartFrm := true.B + } .elsewhen(io.SyncRxStartFrmSyncb){ + LatchedRxStartFrm := false.B + } + + + // Generation of the end-of-frame signal + when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){ + ShiftEnded_rck := true.B + } .elsewhen(io.RxAbort | io.ShiftEndedSyncb & RegNext(io.ShiftEndedSyncb, false.B) ){ + ShiftEnded_rck := false.B + } + + // Generation of the end-of-frame signal + when(io.RxStartFrm){ + RxEnableWindow := true.B + } .elsewhen(io.RxEndFrm | io.RxAbort){ + RxEnableWindow := false.B + } + + + when(io.RxAbortSyncb){ + RxAbortLatched := false.B + } .elsewhen(io.RxAbort){ + RxAbortLatched := true.B + } + + when(io.RxValid & io.RxStartFrm & ~io.RxReady){ + Busy_IRQ_rck := true.B + } .elsewhen(io.Busy_IRQ_syncb){ + Busy_IRQ_rck := false.B + } + + +} + + + diff --git a/src/main/scala/mac/MacTileLinkTx.scala b/src/main/scala/mac/MacTileLinkTx.scala new file mode 100644 index 0000000..1731d1f --- /dev/null +++ b/src/main/scala/mac/MacTileLinkTx.scala @@ -0,0 +1,141 @@ +package MAC + +import chisel3._ +import chisel3.util._ + + +class MacTileLinkTxIO extends Bundle{ + val RstDeferLatched = Output(Bool()) + val BlockingTxStatusWrite_sync = Input(Bool()) + val TxStartFrm_sync = Input(Bool()) + + val TxStartFrm = Output(Bool()) // Transmit packet start frame + val TxEndFrm = Output(Bool()) // Transmit packet end frame + val TxData = Output(UInt(8.W)) // Transmit packet data byte + val TxUnderRun = Output(Bool()) // Transmit packet under-run + + val TxUsedData = Input(Bool()) // Transmit packet used data + val TxRetry = Input(Bool()) // Transmit packet retry + val TxAbort = Input(Bool()) // Transmit packet abort + val TxDone = Input(Bool()) // Transmission ended + + val ReadTxDataFromFifo_tck = Output(Bool()) + val ReadTxDataFromFifo_syncb = Input(Bool()) + + val TxEndFrm_wb = Input(Bool()) + val TxValidBytesLatched = Input(UInt(2.W)) + val TxData_wb = Input(UInt(32.W)) + val TxUnderRun_wb = Input(Bool()) +} + + + +class MacTileLinkTx extends Module with RequireAsyncReset{ + val io = IO(new MacTileLinkTxIO) + + + + io.RstDeferLatched := io.BlockingTxStatusWrite_sync & ~RegNext(io.BlockingTxStatusWrite_sync, false.B) + + val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm + val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm + val TxData = RegInit(0.U(8.W)); io.TxData := TxData + val TxUnderRun = RegInit(false.B); io.TxUnderRun := TxUnderRun + val TxDataLatched = RegInit(0.U(32.W)) + val TxByteCnt = RegInit(0.U(2.W)) + val LastWord = RegInit(false.B) + val ReadTxDataFromFifo_tck = RegInit(false.B); io.ReadTxDataFromFifo_tck := ReadTxDataFromFifo_tck + + // Generating delayed signals + val TxAbort_q = RegNext( io.TxAbort, false.B) + val TxRetry_q = RegNext( io.TxRetry, false.B) + val TxUsedData_q = RegNext( io.TxUsedData, false.B) + + // Changes for tx occur every second clock. Flop is used for this manner. + val Flop = RegInit(false.B) + when( io.TxDone | io.TxAbort | TxRetry_q){ + Flop := false.B + } .elsewhen ( io.TxUsedData ){ + Flop := ~Flop + } + + when(io.TxStartFrm_sync){ + TxStartFrm := true.B + } .elsewhen(TxUsedData_q | ~io.TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){ + TxStartFrm := false.B + } + + // Indication of the last word + when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){ + LastWord := false.B + } .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){ + LastWord := io.TxEndFrm_wb + } + + // Tx end frame generation + when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){ + TxEndFrm := false.B + } .elsewhen(Flop & LastWord){ + TxEndFrm := + Mux1H(Seq( + (io.TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U), + (io.TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U), + (io.TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U), + (io.TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U), + )) + } + + // Tx data selection (latching) + when( io.TxStartFrm_sync & ~TxStartFrm ){ + TxData := io.TxData_wb( 7, 0) // little Endian Byte Ordering + } .elsewhen(io.TxUsedData & Flop){ + TxData := Mux1H(Seq( + (TxByteCnt === 0.U) -> TxDataLatched( 7, 0),// little Endian Byte Ordering + (TxByteCnt === 1.U) -> TxDataLatched(15, 8), + (TxByteCnt === 2.U) -> TxDataLatched(23,16), + (TxByteCnt === 3.U) -> TxDataLatched(31,24), + )) + } + + // Latching tx data + when( + io.TxStartFrm_sync & ~TxStartFrm | + io.TxUsedData & Flop & TxByteCnt === 3.U | + TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){ + TxDataLatched := io.TxData_wb + } + + val TxUnderRun_sync1 = RegInit(false.B) + + // Tx under run + when(io.TxUnderRun_wb){ + TxUnderRun_sync1 := true.B + } .elsewhen(io.BlockingTxStatusWrite_sync){ + TxUnderRun_sync1 := false.B + } + + // Tx under run + when(io.BlockingTxStatusWrite_sync){ + TxUnderRun := false.B + } .elsewhen(TxUnderRun_sync1){ + TxUnderRun := true.B + } + + // Tx Byte counter + when(TxAbort_q | TxRetry_q){ + TxByteCnt := 0.U + } .elsewhen(TxStartFrm & ~io.TxUsedData){ + TxByteCnt := 1.U + } .elsewhen(io.TxUsedData & Flop){ + TxByteCnt := TxByteCnt + 1.U + } + + when(io.TxStartFrm_sync & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U & + ~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){ + ReadTxDataFromFifo_tck := true.B + } .elsewhen(io.ReadTxDataFromFifo_syncb & ~RegNext(io.ReadTxDataFromFifo_syncb, false.B)){ + ReadTxDataFromFifo_tck := false.B + } + +} + diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala index 46e24d3..f066846 100644 --- a/src/main/scala/mac/MacTilelink.scala +++ b/src/main/scala/mac/MacTilelink.scala @@ -52,15 +52,11 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val CarrierSenseLost = Input(Bool()) // Carrier Sense was lost during the frame transmission // Tx - val MTxClk = Input(Bool()) // Transmit clock (from PHY) val TxUsedData = Input(Bool()) // Transmit packet used data val TxUnderRun = Input(Bool()) // Transmit packet under-run val PerPacketCrcEn = Output(Bool()) // Per packet crc enable val PerPacketPad = Output(Bool()) // Per packet pading - // Rx - val MRxClk = Input(Bool()) // Receive clock (from PHY) - //Register val r_TxEn = Input(Bool()) // Transmit enable val r_RxEn = Input(Bool()) // Receive enable @@ -73,8 +69,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val RxE_IRQ = Output(Bool()) val Busy_IRQ = Output(Bool()) - val asyncReset = Input(AsyncReset()) - val BlockingTxStatusWrite = Output(Bool()) @@ -179,8 +173,8 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val ShiftEnded = RegInit(false.B) val RxOverrun = RegInit(false.B) - val BDWrite = RegInit(0.U(4.W)) // BD Write Enable for access from WISHBONE side - val BDRead = RegInit(false.B) // BD Read access from WISHBONE side + val BDWrite = RegInit(0.U(4.W)) // BD Write Enable for access from WISHBONE side + val BDRead = RegInit(false.B) // BD Read access from WISHBONE side val RxBDDataIn = Wire(UInt(32.W)) // Rx BD data in val TxBDDataIn = Wire(UInt(32.W)) // Tx BD data in @@ -206,12 +200,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod // Delayed stage signals - // val WbEn = RegInit(true.B) - // val WbEn_q = RegNext(WbEn, false.B) - // val RxEn = RegInit(false.B) - // val RxEn_q = RegNext(RxEn, false.B) - // val TxEn = RegInit(false.B) - // val TxEn_q = RegNext(TxEn, false.B) val r_TxEn_q = RegNext(io.r_TxEn, false.B) val r_RxEn_q = RegNext(io.r_RxEn, false.B) @@ -982,19 +970,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod io.tlSlv.A.ready := BDAck assert( ~(io.tlSlv.A.ready & ~io.tlSlv.A.valid) ) - // when( io.tlSlv.A.fire & (~(io.tlSlv.A.bits.mask.orR) | CsMiss) ){ - // assert( false.B, "Assert Failed, tileLink access an undefine region!" ) - // } - - - - - - - - - - @@ -1004,12 +979,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val mstABits = Reg(new TLBundleA(edgeOut.bundle)) - - // val tlMstStateDnxt = WireDefault() - // val tlMstState = RegNext( ) - - - when( io.tlMst.A.fire ){ mstAValid := false.B } @@ -1074,533 +1043,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod - - - - - - - - - -} - - -trait MacTileLinkTXClk{ this: MacTileLinkBase => - - // val macTileLinkTX = withClockAndReset( io.MTxClk.asClock, io.asyncReset ) (Module(new MacTileLinkTX)) - - // withClockAndReset( io.MTxClk.asClock, io.asyncReset ){ - // macTileLinkTX.io.BlockingTxStatusWrite_sync := ShiftRegister(BlockingTxStatusWrite, 2, false.B, true.B) - // macTileLinkTX.io.TxStartFrm_sync := ShiftRegister( TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk - // macTileLinkTX.io.ReadTxDataFromFifo_syncb := ShiftRegister(ReadTxDataFromFifo_sync(1), 2, false.B, true.B) - // } - - - // TxStartFrm_syncb := ShiftRegister( macTileLinkTX.io.TxStartFrm_sync, 2, false.B, true.B ) - - // io.RstDeferLatched := macTileLinkTX.io.RstDeferLatched - // io.TxStartFrm := macTileLinkTX.io.TxStartFrm - // io.TxEndFrm := macTileLinkTX.io.TxEndFrm - // io.TxData := macTileLinkTX.io.TxData - // io.TxUnderRun := macTileLinkTX.io.TxUnderRun - - // macTileLinkTX.io.TxUnderRun_wb := TxUnderRun_wb - // macTileLinkTX.io.TxData_wb := TxData_wb - // macTileLinkTX.io.TxValidBytesLatched := TxValidBytesLatched - // macTileLinkTX.io.TxEndFrm_wb := TxEndFrm_wb - - // ReadTxDataFromFifo_tck_txclk := macTileLinkTX.io.ReadTxDataFromFifo_tck - - // macTileLinkTX.io.TxUsedData := io.TxUsedData - // macTileLinkTX.io.TxRetry := io.TxRetry - // macTileLinkTX.io.TxAbort := io.TxAbort - // macTileLinkTX.io.TxDone := io.TxDone -} - - - - -trait MacTileLinkRXClk{ this: MacTileLinkBase => - // val macTileLinkRX = withClockAndReset( io.MRxClk.asClock, io.asyncReset ) ( Module(new MacTileLinkRX) ) - // RxDataLatched2_rxclk := macTileLinkRX.io.RxDataLatched2 - // WriteRxDataToFifo_rxclk := macTileLinkRX.io.WriteRxDataToFifo - // RxAbortLatched_rxclk := macTileLinkRX.io.RxAbortLatched - // LatchedRxLength_rxclk := macTileLinkRX.io.LatchedRxLength - // RxStatusInLatched_rxclk := macTileLinkRX.io.RxStatusInLatched - // ShiftEnded_rck_rxclk := macTileLinkRX.io.ShiftEnded_rck - // LatchedRxStartFrm_rxclk := macTileLinkRX.io.LatchedRxStartFrm - - - - // // Busy Interrupt - // val Busy_IRQ_sync = ShiftRegisters(macTileLinkRX.io.Busy_IRQ_rck, 3) - // io.Busy_IRQ := Busy_IRQ_sync(1) & ~Busy_IRQ_sync(2) - - // withClockAndReset( io.MRxClk.asClock, io.asyncReset ) { - // macTileLinkRX.io.ShiftEndedSync := ShiftRegisters(ShiftEndedSync(1), 2, false.B, true.B) - // macTileLinkRX.io.RxAbortSyncb := ShiftRegister( RxAbortSync(1), 2, false.B, true.B ) - // io.RxStatusWriteLatched_sync2 := ShiftRegister(RxStatusWriteLatched, 2, false.B, true.B) - // macTileLinkRX.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync(1), 2, false.B, true.B ) - - // macTileLinkRX.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync(1), 2, false.B, true.B ) - // macTileLinkRX.io.SyncRxStartFrmSyncb := ShiftRegister( SyncRxStartFrmSync(1), 2, false.B, true.B ) - // macTileLinkRX.io.RxReady := ShiftRegister( RxReady, 2, false.B, true.B ) - // } - - // macTileLinkRX.io.RxData := io.RxData - // macTileLinkRX.io.RxAbort := io.RxAbort - // macTileLinkRX.io.RxValid := io.RxValid - - // macTileLinkRX.io.RxStartFrm := io.RxStartFrm - // macTileLinkRX.io.RxEndFrm := io.RxEndFrm - - - // macTileLinkRX.io.RxLength := io.RxLength - // macTileLinkRX.io.LoadRxStatus := io.LoadRxStatus - // macTileLinkRX.io.RxStatusIn := RxStatusIn - -} - - -class MacTileLink(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends MacTileLinkBase(edgeIn, edgeOut) with MacTileLinkTXClk with MacTileLinkRXClk - - - - - - -class MacTileLinkTXIO extends Bundle{ - val RstDeferLatched = Output(Bool()) - val BlockingTxStatusWrite_sync = Input(Bool()) - val TxStartFrm_sync = Input(Bool()) - - val TxStartFrm = Output(Bool()) // Transmit packet start frame - val TxEndFrm = Output(Bool()) // Transmit packet end frame - val TxData = Output(UInt(8.W)) // Transmit packet data byte - val TxUnderRun = Output(Bool()) // Transmit packet under-run - - val TxUsedData = Input(Bool()) // Transmit packet used data - val TxRetry = Input(Bool()) // Transmit packet retry - val TxAbort = Input(Bool()) // Transmit packet abort - val TxDone = Input(Bool()) // Transmission ended - - val ReadTxDataFromFifo_tck = Output(Bool()) - val ReadTxDataFromFifo_syncb = Input(Bool()) - - val TxEndFrm_wb = Input(Bool()) - val TxValidBytesLatched = Input(UInt(2.W)) - val TxData_wb = Input(UInt(32.W)) - val TxUnderRun_wb = Input(Bool()) -} - - - -class MacTileLinkTX extends Module with RequireAsyncReset{ - val io = IO(new MacTileLinkTXIO) - - - - io.RstDeferLatched := io.BlockingTxStatusWrite_sync & ~RegNext(io.BlockingTxStatusWrite_sync, false.B) - - val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm - val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm - val TxData = RegInit(0.U(8.W)); io.TxData := TxData - val TxUnderRun = RegInit(false.B); io.TxUnderRun := TxUnderRun - val TxDataLatched = RegInit(0.U(32.W)) - val TxByteCnt = RegInit(0.U(2.W)) - val LastWord = RegInit(false.B) - val ReadTxDataFromFifo_tck = RegInit(false.B); io.ReadTxDataFromFifo_tck := ReadTxDataFromFifo_tck - - // Generating delayed signals - val TxAbort_q = RegNext( io.TxAbort, false.B) - val TxRetry_q = RegNext( io.TxRetry, false.B) - val TxUsedData_q = RegNext( io.TxUsedData, false.B) - - // Changes for tx occur every second clock. Flop is used for this manner. - val Flop = RegInit(false.B) - when( io.TxDone | io.TxAbort | TxRetry_q){ - Flop := false.B - } .elsewhen ( io.TxUsedData ){ - Flop := ~Flop - } - - when(io.TxStartFrm_sync){ - TxStartFrm := true.B - } .elsewhen(TxUsedData_q | ~io.TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){ - TxStartFrm := false.B - } - - // Indication of the last word - when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){ - LastWord := false.B - } .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){ - LastWord := io.TxEndFrm_wb - } - - // Tx end frame generation - when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){ - TxEndFrm := false.B - } .elsewhen(Flop & LastWord){ - TxEndFrm := - Mux1H(Seq( - (io.TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U), - (io.TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U), - (io.TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U), - (io.TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U), - )) - } - - // Tx data selection (latching) - when( io.TxStartFrm_sync & ~TxStartFrm ){ - TxData := io.TxData_wb( 7, 0) // little Endian Byte Ordering - } .elsewhen(io.TxUsedData & Flop){ - TxData := Mux1H(Seq( - (TxByteCnt === 0.U) -> TxDataLatched( 7, 0),// little Endian Byte Ordering - (TxByteCnt === 1.U) -> TxDataLatched(15, 8), - (TxByteCnt === 2.U) -> TxDataLatched(23,16), - (TxByteCnt === 3.U) -> TxDataLatched(31,24), - )) - } - - // Latching tx data - when( - io.TxStartFrm_sync & ~TxStartFrm | - io.TxUsedData & Flop & TxByteCnt === 3.U | - TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){ - TxDataLatched := io.TxData_wb - } - - val TxUnderRun_sync1 = RegInit(false.B) - - // Tx under run - when(io.TxUnderRun_wb){ - TxUnderRun_sync1 := true.B - } .elsewhen(io.BlockingTxStatusWrite_sync){ - TxUnderRun_sync1 := false.B - } - - // Tx under run - when(io.BlockingTxStatusWrite_sync){ - TxUnderRun := false.B - } .elsewhen(TxUnderRun_sync1){ - TxUnderRun := true.B - } - - // Tx Byte counter - when(TxAbort_q | TxRetry_q){ - TxByteCnt := 0.U - } .elsewhen(TxStartFrm & ~io.TxUsedData){ - TxByteCnt := 1.U - } .elsewhen(io.TxUsedData & Flop){ - TxByteCnt := TxByteCnt + 1.U - } - - when(io.TxStartFrm_sync & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U & - ~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){ - ReadTxDataFromFifo_tck := true.B - } .elsewhen(io.ReadTxDataFromFifo_syncb & ~RegNext(io.ReadTxDataFromFifo_syncb, false.B)){ - ReadTxDataFromFifo_tck := false.B - } - -} - - - - - -// trait MacTileLinkTXClk{ this: MacTileLinkBase => -// withClockAndReset( io.MTxClk.asClock, io.asyncReset ) { - -// val Flop = RegInit(false.B) - -// val BlockingTxStatusWrite_sync = ShiftRegisters(BlockingTxStatusWrite, 3, false.B, true.B) // Synchronizing BlockingTxStatusWrite to MTxClk - -// io.RstDeferLatched := BlockingTxStatusWrite_sync(1) & ~BlockingTxStatusWrite_sync(2) - - - -// val TxStartFrm_sync = ShiftRegister( TxStartFrm_wb, 2, false.B, true.B ); TxStartFrm_sync_txclk := TxStartFrm_sync// Synchronizing TxStartFrm_wb to MTxClk - -// val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm -// val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm -// val TxData = RegInit(0.U(8.W)); io.TxData := TxData -// val TxUnderRun = RegInit(false.B); io.TxUnderRun := TxUnderRun -// val TxDataLatched = RegInit(0.U(32.W)) -// val TxByteCnt = RegInit(0.U(2.W)) -// val LastWord = RegInit(false.B) -// val ReadTxDataFromFifo_tck = RegInit(false.B); ReadTxDataFromFifo_tck_txclk := ReadTxDataFromFifo_tck - -// // Generating delayed signals -// val TxAbort_q = RegNext( io.TxAbort, false.B) -// val TxRetry_q = RegNext( io.TxRetry, false.B) -// val TxUsedData_q = RegNext( io.TxUsedData, false.B) - -// val ReadTxDataFromFifo_syncb = ShiftRegisters(ReadTxDataFromFifo_sync(1), 3, false.B, true.B) - -// // Changes for tx occur every second clock. Flop is used for this manner. -// when( io.TxDone | io.TxAbort | TxRetry_q){ -// Flop := false.B -// } .elsewhen ( io.TxUsedData ){ -// Flop := ~Flop -// } - -// when(TxStartFrm_sync){ -// TxStartFrm := true.B -// } .elsewhen(TxUsedData_q | ~TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){ -// TxStartFrm := false.B -// } - - -// // Indication of the last word -// when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){ -// LastWord := false.B -// } .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){ -// LastWord := TxEndFrm_wb -// } - -// // Tx end frame generation -// when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){ -// TxEndFrm := false.B -// } .elsewhen(Flop & LastWord){ -// TxEndFrm := -// Mux1H(Seq( -// (TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U), -// (TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U), -// (TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U), -// (TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U), -// )) -// } - - - -// // Tx data selection (latching) -// when( TxStartFrm_sync & ~TxStartFrm ){ -// TxData := TxData_wb( 7, 0) // little Endian Byte Ordering -// } .elsewhen(io.TxUsedData & Flop){ -// TxData := Mux1H(Seq( -// (TxByteCnt === 0.U) -> TxDataLatched( 7, 0),// little Endian Byte Ordering -// (TxByteCnt === 1.U) -> TxDataLatched(15, 8), -// (TxByteCnt === 2.U) -> TxDataLatched(23,16), -// (TxByteCnt === 3.U) -> TxDataLatched(31,24), -// )) -// } - - - -// // Latching tx data -// when( -// TxStartFrm_sync & ~TxStartFrm | -// io.TxUsedData & Flop & TxByteCnt === 3.U | -// TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){ -// TxDataLatched := TxData_wb -// } - - -// val TxUnderRun_sync1 = RegInit(false.B) - -// // Tx under run -// when(TxUnderRun_wb){ -// TxUnderRun_sync1 := true.B -// } .elsewhen(BlockingTxStatusWrite_sync(1)){ -// TxUnderRun_sync1 := false.B -// } - - -// // Tx under run -// when(BlockingTxStatusWrite_sync(1)){ -// TxUnderRun := false.B -// } .elsewhen(TxUnderRun_sync1){ -// TxUnderRun := true.B -// } - - - -// // Tx Byte counter -// when(TxAbort_q | TxRetry_q){ -// TxByteCnt := 0.U -// } .elsewhen(TxStartFrm & ~io.TxUsedData){ -// TxByteCnt := 1.U -// } .elsewhen(io.TxUsedData & Flop){ -// TxByteCnt := TxByteCnt + 1.U -// } - -// when(TxStartFrm_sync & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U & -// ~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){ -// ReadTxDataFromFifo_tck := true.B -// } .elsewhen(ReadTxDataFromFifo_syncb(1) & ~ReadTxDataFromFifo_syncb(2)){ -// ReadTxDataFromFifo_tck := false.B -// } - - -// } -// } - - - - - - - - - -class MacTileLinkRXIO extends Bundle{ - val RxDataLatched2 = Output(UInt(32.W)) - val WriteRxDataToFifo = Output(Bool()) - val RxAbortLatched = Output(Bool()) - val LatchedRxLength = Output(UInt(16.W)) - val RxStatusInLatched = Output( UInt(9.W) ) - val ShiftEnded_rck = Output(Bool()) - val LatchedRxStartFrm = Output(Bool()) - - val RxLength = Input(UInt(16.W)) - val LoadRxStatus = Input(Bool()) - val RxStatusIn = Input(UInt(9.W)) - val ShiftEndedSyncb = Input(Bool()) - val RxAbortSyncb = Input(Bool()) - val WriteRxDataToFifoSyncb = Input(Bool()) - val SyncRxStartFrmSyncb = Input(Bool()) - - val Busy_IRQ_rck = Output(Bool()) - val Busy_IRQ_syncb = Input(Bool()) - - val RxData = Input(UInt(8.W)) // Received data byte (from PHY) - val RxAbort = Input(Bool()) - val RxValid = Input(Bool()) - val RxReady = Input(Bool()) - val RxStartFrm = Input(Bool()) - val RxEndFrm = Input(Bool()) -} - - -class MacTileLinkRX extends Module with RequireAsyncReset{ - val io = IO(new MacTileLinkRXIO) - - val RxDataLatched2 = RegInit(0.U(32.W)); io.RxDataLatched2 := RxDataLatched2 - val RxDataLatched1 = RegInit(0.U(24.W)) // Little Endian Byte Ordering[23:0] - val RxValidBytes = RegInit(1.U(2.W)) - val RxByteCnt = RegInit(0.U(2.W)) - val LastByteIn = RegInit(false.B) - val ShiftWillEnd = RegInit(false.B) - val WriteRxDataToFifo = RegInit(false.B); io.WriteRxDataToFifo := WriteRxDataToFifo - val RxAbortLatched = RegInit(false.B); io.RxAbortLatched := RxAbortLatched - - val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength - val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched - - val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck - val RxEnableWindow = RegInit(false.B) - - val LatchedRxStartFrm = RegInit(false.B); io.LatchedRxStartFrm := LatchedRxStartFrm - - val Busy_IRQ_rck = RegInit(false.B); io.Busy_IRQ_rck := Busy_IRQ_rck - - - - - // Indicating that last byte is being reveived - when(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){ - LastByteIn := false.B - } .elsewhen(io.RxValid & io.RxReady & io.RxEndFrm & ~(RxByteCnt.andR) & RxEnableWindow){ - LastByteIn := true.B - } - - // Indicating that data reception will end - val StartShiftWillEnd = LastByteIn | io.RxValid & io.RxEndFrm & RxByteCnt.andR & RxEnableWindow - when(ShiftEnded_rck | io.RxAbort){ - ShiftWillEnd := false.B - } .elsewhen(StartShiftWillEnd){ - ShiftWillEnd := true.B - } - - // Receive byte counter - when(ShiftEnded_rck | io.RxAbort){ - RxByteCnt := 0.U - } .elsewhen(io.RxValid & io.RxStartFrm & io.RxReady){ - RxByteCnt := 1.U - } .elsewhen(io.RxValid & RxEnableWindow & io.RxReady | LastByteIn){ - RxByteCnt := RxByteCnt + 1.U - } - - // Indicates how many bytes are valid within the last word - when(io.RxValid & io.RxStartFrm){ - RxValidBytes := 1.U - } .elsewhen(io.RxValid & ~LastByteIn & ~io.RxStartFrm & RxEnableWindow){ - RxValidBytes := RxValidBytes + 1.U - } - - when(io.RxValid & io.RxReady & ~LastByteIn){ - when(io.RxStartFrm){ - RxDataLatched1 := Cat(RxDataLatched1(23, 8), io.RxData)// Little Endian Byte Ordering - } .elsewhen(RxEnableWindow){ - RxDataLatched1 := Mux1H(Seq( - ( RxByteCnt === 0.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),// Little Endian Byte Ordering - ( RxByteCnt === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)), - ( RxByteCnt === 2.U ) -> Cat( io.RxData, RxDataLatched1(15,0)), - ( RxByteCnt === 3.U ) -> RxDataLatched1, - )) - } - } - - // Indicating start of the reception process - val SetWriteRxDataToFifo = - (io.RxValid & io.RxReady & ~io.RxStartFrm & RxEnableWindow & (RxByteCnt.andR)) | - (ShiftWillEnd & LastByteIn & (RxByteCnt.andR)) - - // Assembling data that will be written to the rx_fifo - when(SetWriteRxDataToFifo & ~ShiftWillEnd){ - RxDataLatched2 := Cat(io.RxData, RxDataLatched1)// Little Endian Byte Ordering - } .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){ - RxDataLatched2 := Mux1H(Seq( // Little Endian Byte Ordering - ( RxValidBytes === 0.U ) -> Cat(io.RxData, RxDataLatched1), - ( RxValidBytes === 1.U ) -> Cat(0.U(24.W), RxDataLatched1(7,0) ), - ( RxValidBytes === 2.U ) -> Cat(0.U(16.W), RxDataLatched1(15, 0) ), - ( RxValidBytes === 3.U ) -> Cat(0.U(8.W), RxDataLatched1 ), - )) - } - - when(SetWriteRxDataToFifo & ~io.RxAbort){ - WriteRxDataToFifo := true.B - } .elsewhen(io.WriteRxDataToFifoSyncb | io.RxAbort){ - WriteRxDataToFifo := false.B - } - - - when(io.RxStartFrm & ~io.SyncRxStartFrmSyncb){ - LatchedRxStartFrm := true.B - } .elsewhen(io.SyncRxStartFrmSyncb){ - LatchedRxStartFrm := false.B - } - - - // Generation of the end-of-frame signal - when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){ - ShiftEnded_rck := true.B - } .elsewhen(io.RxAbort | io.ShiftEndedSyncb & RegNext(io.ShiftEndedSyncb, false.B) ){ - ShiftEnded_rck := false.B - } - - // Generation of the end-of-frame signal - when(io.RxStartFrm){ - RxEnableWindow := true.B - } .elsewhen(io.RxEndFrm | io.RxAbort){ - RxEnableWindow := false.B - } - - - when(io.RxAbortSyncb){ - RxAbortLatched := false.B - } .elsewhen(io.RxAbort){ - RxAbortLatched := true.B - } - - when(io.RxValid & io.RxStartFrm & ~io.RxReady){ - Busy_IRQ_rck := true.B - } .elsewhen(io.Busy_IRQ_syncb){ - Busy_IRQ_rck := false.B - } - - } @@ -1608,6 +1050,7 @@ class MacTileLinkRX extends Module with RequireAsyncReset{ +class MacTileLink(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends MacTileLinkBase(edgeIn, edgeOut) @@ -1624,144 +1067,6 @@ class MacTileLinkRX extends Module with RequireAsyncReset{ - - -// trait MacTileLinkRXClk{ this: MacTileLinkBase => - -// withClockAndReset( io.MRxClk.asClock, io.asyncReset ){ - -// val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2 -// val RxDataLatched1 = RegInit(0.U(24.W)) // Little Endian Byte Ordering[23:0] -// val RxValidBytes = RegInit(1.U(2.W)) -// val RxByteCnt = RegInit(0.U(2.W)); RxByteCnt_rxclk := RxByteCnt -// val LastByteIn = RegInit(false.B); LastByteIn_rxclk := LastByteIn -// val ShiftWillEnd = RegInit(false.B); ShiftWillEnd_rxclk := ShiftWillEnd -// val WriteRxDataToFifo = RegInit(false.B); WriteRxDataToFifo_rxclk := WriteRxDataToFifo -// val RxAbortLatched = RegInit(false.B); RxAbortLatched_rxclk := RxAbortLatched - -// val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); LatchedRxLength_rxclk := LatchedRxLength -// val RxStatusInLatched = RegEnable(RxStatusIn, 0.U(9.W), io.LoadRxStatus); RxStatusInLatched_rxclk := RxStatusInLatched -// val ShiftEnded_rck = RegInit(false.B); ShiftEnded_rck_txclk := ShiftEnded_rck - -// val ShiftEndedSyncb = ShiftRegisters(ShiftEndedSync2, 2, false.B, true.B) - -// val RxAbortSyncb = ShiftRegister( RxAbortSync(1), 2, false.B, true.B ) - -// val RxEnableWindow = RegInit(false.B); RxEnableWindow_rxclk := RxEnableWindow -// val LatchedRxStartFrm = RegInit(false.B); LatchedRxStartFrm_rxclk := LatchedRxStartFrm - -// val RxStatusWriteLatched_sync = ShiftRegister(RxStatusWriteLatched, 2, false.B, true.B); io.RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync -// // Indicating that last byte is being reveived - -// when(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){ -// LastByteIn := false.B -// } .elsewhen(io.RxValid & RxReady & io.RxEndFrm & ~(RxByteCnt.andR) & RxEnableWindow){ -// LastByteIn := true.B -// } - -// // Indicating that data reception will end -// when(ShiftEnded_rck | io.RxAbort){ -// ShiftWillEnd := false.B -// } .elsewhen(StartShiftWillEnd){ -// ShiftWillEnd := true.B -// } - -// // Receive byte counter -// when(ShiftEnded_rck | io.RxAbort){ -// RxByteCnt := 0.U -// } .elsewhen(io.RxValid & io.RxStartFrm & RxReady){ -// RxByteCnt := 1.U -// } .elsewhen(io.RxValid & RxEnableWindow & RxReady | LastByteIn){ -// RxByteCnt := RxByteCnt + 1.U -// } - -// // Indicates how many bytes are valid within the last word -// when(io.RxValid & io.RxStartFrm){ -// RxValidBytes := 1.U -// } .elsewhen(io.RxValid & ~LastByteIn & ~io.RxStartFrm & RxEnableWindow){ -// RxValidBytes := RxValidBytes + 1.U -// } - -// when(io.RxValid & RxReady & ~LastByteIn){ -// when(io.RxStartFrm){ -// RxDataLatched1 := Cat(RxDataLatched1(23, 8), io.RxData)// Little Endian Byte Ordering -// } .elsewhen(RxEnableWindow){ -// RxDataLatched1 := Mux1H(Seq( -// ( RxByteCnt === 0.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),// Little Endian Byte Ordering -// ( RxByteCnt === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)), -// ( RxByteCnt === 2.U ) -> Cat( io.RxData, RxDataLatched1(15,0)), -// ( RxByteCnt === 3.U ) -> RxDataLatched1, -// )) -// } -// } - - -// // Assembling data that will be written to the rx_fifo -// when(SetWriteRxDataToFifo & ~ShiftWillEnd){ -// RxDataLatched2 := Cat(io.RxData, RxDataLatched1)// Little Endian Byte Ordering -// } .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){ -// RxDataLatched2 := Mux1H(Seq( // Little Endian Byte Ordering -// ( RxValidBytes === 0.U ) -> Cat(io.RxData, RxDataLatched1), -// ( RxValidBytes === 1.U ) -> Cat(0.U(24.W), RxDataLatched1(7,0) ), -// ( RxValidBytes === 2.U ) -> Cat(0.U(16.W), RxDataLatched1(15, 0) ), -// ( RxValidBytes === 3.U ) -> Cat(0.U(8.W), RxDataLatched1 ), -// )) -// } - -// when(SetWriteRxDataToFifo & ~io.RxAbort){ -// WriteRxDataToFifo := true.B -// } .elsewhen(WriteRxDataToFifoSync(1) | io.RxAbort){ -// WriteRxDataToFifo := false.B -// } - - -// when(io.RxStartFrm & ~SyncRxStartFrm(1)){ -// LatchedRxStartFrm := true.B -// } .elsewhen(SyncRxStartFrm(1)){ -// LatchedRxStartFrm := false.B -// } - - -// // Generation of the end-of-frame signal -// when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){ -// ShiftEnded_rck := true.B -// } .elsewhen(io.RxAbort | ShiftEndedSyncb(0) & ShiftEndedSyncb(1)){ -// ShiftEnded_rck := false.B -// } - -// // Generation of the end-of-frame signal -// when(io.RxStartFrm){ -// RxEnableWindow := true.B -// } .elsewhen(io.RxEndFrm | io.RxAbort){ -// RxEnableWindow := false.B -// } - - -// when(RxAbortSyncb){ -// RxAbortLatched := false.B -// } .elsewhen(io.RxAbort){ -// RxAbortLatched := true.B -// } - - - - - - - -// val Busy_IRQ_rck = RegInit(false.B); Busy_IRQ_rck_rxclk := Busy_IRQ_rck -// val Busy_IRQ_syncb = ShiftRegister( Busy_IRQ_sync(1), 2, false.B, true.B ) - -// when(io.RxValid & io.RxStartFrm & ~RxReady){ -// Busy_IRQ_rck := true.B -// } .elsewhen(Busy_IRQ_syncb){ -// Busy_IRQ_rck := false.B -// } - - - -// } -// }