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bug清理完成

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This commit is contained in:
RuigeLee
2023-10-26 15:46:21 +08:00
parent 530e6d9792
commit ada2f25ff3
1 changed files with 9 additions and 9 deletions
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18
src/main/scala/Switch/mac/MacTileLinkTx.scala
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@@ -42,7 +42,7 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
val TxData = RegInit(0.U(8.W)); io.TxData := TxData
val LastWord = RegInit(false.B)
// val LastWord = RegInit(false.B)
val ReadTxDataFromFifo_tck = RegInit(false.B);
// Generating delayed signals
@@ -63,17 +63,17 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
TxStartFrm := false.B
}
// Indication of the last word
when( (TxEndFrm | io.TxAbort) & Flop ){
LastWord := false.B
} .elsewhen( io.txReq.fire ){
LastWord := io.txReq.bits.isLast
}
// // Indication of the last word
// when( (TxEndFrm | io.TxAbort) & Flop ){
// LastWord := false.B
// } .elsewhen( io.txReq.fire ){
// LastWord := io.txReq.bits.isLast
// }
// Tx end frame generation
when(Flop & TxEndFrm | io.TxAbort){
TxEndFrm := false.B
} .elsewhen(Flop & LastWord){
} .elsewhen( io.txReq.fire & io.txReq.bits.isLast ){
TxEndFrm := true.B
}
@@ -81,7 +81,7 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
io.txReq.ready :=
io.txReq.valid & io.txReq.bits.isStart & ~TxStartFrm |
io.TxUsedData & Flop & ~LastWord |
io.TxUsedData & Flop & ~TxEndFrm |
TxStartFrm & io.TxUsedData & Flop
when( io.txReq.fire ){