From ada2f25ff37d850d4dbc7aa31061bdd788f082ba Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 26 Oct 2023 15:46:21 +0800 Subject: [PATCH] =?UTF-8?q?bug=E6=B8=85=E7=90=86=E5=AE=8C=E6=88=90?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/Switch/mac/MacTileLinkTx.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/Switch/mac/MacTileLinkTx.scala b/src/main/scala/Switch/mac/MacTileLinkTx.scala index 68bbb5f..94693ce 100644 --- a/src/main/scala/Switch/mac/MacTileLinkTx.scala +++ b/src/main/scala/Switch/mac/MacTileLinkTx.scala @@ -42,7 +42,7 @@ class MacTileLinkTx extends Module with RequireAsyncReset{ val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm val TxData = RegInit(0.U(8.W)); io.TxData := TxData - val LastWord = RegInit(false.B) + // val LastWord = RegInit(false.B) val ReadTxDataFromFifo_tck = RegInit(false.B); // Generating delayed signals @@ -63,17 +63,17 @@ class MacTileLinkTx extends Module with RequireAsyncReset{ TxStartFrm := false.B } - // Indication of the last word - when( (TxEndFrm | io.TxAbort) & Flop ){ - LastWord := false.B - } .elsewhen( io.txReq.fire ){ - LastWord := io.txReq.bits.isLast - } + // // Indication of the last word + // when( (TxEndFrm | io.TxAbort) & Flop ){ + // LastWord := false.B + // } .elsewhen( io.txReq.fire ){ + // LastWord := io.txReq.bits.isLast + // } // Tx end frame generation when(Flop & TxEndFrm | io.TxAbort){ TxEndFrm := false.B - } .elsewhen(Flop & LastWord){ + } .elsewhen( io.txReq.fire & io.txReq.bits.isLast ){ TxEndFrm := true.B } @@ -81,7 +81,7 @@ class MacTileLinkTx extends Module with RequireAsyncReset{ io.txReq.ready := io.txReq.valid & io.txReq.bits.isStart & ~TxStartFrm | - io.TxUsedData & Flop & ~LastWord | + io.TxUsedData & Flop & ~TxEndFrm | TxStartFrm & io.TxUsedData & Flop when( io.txReq.fire ){